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基于NOR Flash的存算一體模擬乘加電路設(shè)計(jì)
信息技術(shù)與網(wǎng)絡(luò)安全
丁士鵬,,黃 魯
(中國(guó)科學(xué)技術(shù)大學(xué) 微電子學(xué)院,安徽 合肥230026)
摘要: 提出一種基于NOR Flash的存算一體模擬乘加電路以及相應(yīng)的偏置電路,,運(yùn)用NOR Flash工作于深線性區(qū)的I-V特性,,實(shí)現(xiàn)模擬乘累加運(yùn)算。通過(guò)將同一位線,、不同字線的兩個(gè)浮柵管上電流相減,,實(shí)現(xiàn)其閾值電壓差值與漏源電壓的乘法運(yùn)算。同時(shí)將同一字線,、不同位線的浮柵管電流相加,,實(shí)現(xiàn)乘法結(jié)果的加法運(yùn)算。給出電路使NOR Flash位線電流相加,、字線電流相減,,將運(yùn)算結(jié)果以偽差分的形式輸出,仿真結(jié)果表明電路可以實(shí)現(xiàn)存算一體的模擬乘累加運(yùn)算,。
中圖分類號(hào): TN432
文獻(xiàn)標(biāo)識(shí)碼: A
DOI: 10.19358/j.issn.2096-5133.2021.06.012
引用格式: 丁士鵬,,黃魯. 基于NOR Flash的存算一體模擬乘加電路設(shè)計(jì)[J].信息技術(shù)與網(wǎng)絡(luò)安全,2021,,40(6):69-74.
Design of an analog multiply accumulate circuit based on NOR Flash
Ding Shipeng,,Huang Lu
(College of Microelectronics,University of Science and Technology of China,,Hefei 230026,,China)
Abstract: This article proposed a NOR Flash-based storage-calculation integrated analog multiply-accumulate circuit and the corresponding bias circuit, using the I-V characteristics of NOR Flash working in deep linear region to realize analog multiply-accumulate operations. Subtracting the current on the two floating gate tubes of the same bit line and different word line, the difference threshold voltage multiplied with the drain-source voltage. And the current on the floating gate tubes of the same word line and different bit lines were added together to realize the addition operation of the multiplication result. This article provided a circuit to add NOR Flash bit line current and subtract word line current, and output the calculation results in the form of pseudo-differential. The simulation result showed that the circuit can realize the analog multiply-accumulate operation of storing and calculating.
Key words : NOR Flash;storage and calculation,;analog multiply and accumulate circuit

0 引言

隨著對(duì)人工智能研究的不斷深入,,深度學(xué)習(xí)正成為訓(xùn)練機(jī)器實(shí)現(xiàn)智能的重要研究方法。在深度學(xué)習(xí)中,,有著大量的輸入數(shù)據(jù),、網(wǎng)絡(luò)參數(shù)以及乘累加運(yùn)算[1]。

在以馮·諾依曼為主流的存算分離架構(gòu)中,,計(jì)算單元與內(nèi)存單元數(shù)據(jù)搬運(yùn)的時(shí)延和功耗開銷越來(lái)越成為深度學(xué)習(xí)神經(jīng)網(wǎng)絡(luò)所面臨的一個(gè)嚴(yán)峻問(wèn)題[2],,嚴(yán)重制約著深度學(xué)習(xí)神經(jīng)網(wǎng)絡(luò)的應(yīng)用。以應(yīng)用深度學(xué)習(xí)神經(jīng)網(wǎng)絡(luò)的AlphaGo為例,,其在進(jìn)行每一局的圍棋活動(dòng)中,,用電成本約為3 000美元[3],對(duì)于大多數(shù)智能設(shè)備而言,,是無(wú)法接受的,。面對(duì)傳統(tǒng)存算架構(gòu)在深度學(xué)習(xí)神經(jīng)網(wǎng)絡(luò)運(yùn)算中的功耗與速度瓶頸,采用存算一體的架構(gòu)成為現(xiàn)階段解決帶寬與功耗問(wèn)題的一條有效途徑,。





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作者信息:

丁士鵬,,黃  魯

(中國(guó)科學(xué)技術(shù)大學(xué) 微電子學(xué)院,,安徽 合肥230026)


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