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基于MIPI規(guī)范的從端D-PHY數(shù)字電路設(shè)計
2021年電子技術(shù)應(yīng)用第11期
張自豪1,,2,,趙建中1,,周玉梅1,,2
1.中國科學(xué)院微電子研究所,,北京100029,;2.中國科學(xué)院大學(xué),,北京100049
摘要: 基于MIPI D-PHY v1.1規(guī)范,,提出了一種從端D-PHY數(shù)字電路設(shè)計,,該從端D-PHY采用4通道實現(xiàn),。高速模式下,,單通道數(shù)據(jù)傳輸速率最高支持1.5 Gb/s;低功耗模式下,,通道0數(shù)據(jù)傳輸速率最高支持10 Mb/s,。高速模式下,串行數(shù)據(jù)流的解串由模擬電路實現(xiàn),,解串后數(shù)據(jù)的幀頭同步檢測由數(shù)字電路實現(xiàn),;D-PHY引導(dǎo)碼的檢測以及低功耗模式下數(shù)據(jù)傳輸為異步通信,提出了一種異步時鐘實現(xiàn)方式,;采用SMIC 0.18 μm CMOS工藝庫進(jìn)行綜合,,典型工藝角下,整體電路的面積為95 061 μm2,;整體功耗為4.291 mW,,其中低功耗模式下功耗為231.3 μW。
中圖分類號: TN492
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.211418
中文引用格式: 張自豪,,趙建中,,周玉梅. 基于MIPI規(guī)范的從端D-PHY數(shù)字電路設(shè)計[J].電子技術(shù)應(yīng)用,2021,,47(11):33-38.
英文引用格式: Zhang Zihao,,Zhao Jianzhong,Zhou Yumei. Design of slave D-PHY digital circuit based on MIPI specification[J]. Application of Electronic Technique,,2021,,47(11):33-38.
Design of slave D-PHY digital circuit based on MIPI specification
Zhang Zihao1,2,,Zhao Jianzhong1,,Zhou Yumei1,2
1.Institute of Microelectronics,,Chinese Academy of Science,,Beijing 100029,China,; 2.University of Chinese Academy of Sciences,,Beijing 100049,China
Abstract: Based on the MIPI D-PHY version 1.1 specification, a design of slave D-PHY digital circuit is proposed, which is implemented with 4 lanes. In the high-speed mode, the data transfer rate of a single lane supports up to 1.5 Gb/s; in the low-power mode, the data transfer rate of lane 0 is up to 10 Mb/s. In the high-speed mode, the deserialization of the serial data stream is implemented by the analog circuit, and the synchronization detection of the data frame header after deserialization is realized by the digital circuit; the detection of the D-PHY entry code and the data transmission in the low-power mode are asynchronous communication and a kind of asynchronous clock implementation is proposed; SMIC 0.18 μm CMOS process library is used for synthesis, and at the typical process corner, the overall circuit area is 95 061 μm2; the overall power consumption is 4.291 mW, and the power consumption in low power mode is 231.3 μW.
Key words : MIPI,;D-PHY,;high speed mode;low-power mode,;asynchronous clock

0 引言

    早在2003年,,ARM、諾基亞、德州儀器和意法半導(dǎo)體四家公司就預(yù)見了智能,、多媒體手機(jī)的廣闊市場前景,,成立了移動產(chǎn)業(yè)處理器接口(Mobile Industry Processor Interface,MIPI)聯(lián)盟[1],。目前,,所有主要的芯片廠商使用MIPI規(guī)范,所有智能手機(jī)都至少使用一種MIPI規(guī)范,。串行顯示接口(Display Serial Interface,,DSI)協(xié)議是MIPI聯(lián)盟推出的針對高速顯示接口的規(guī)范[2],多用于移動終端系統(tǒng)[3],,其特點(diǎn)是高速,、靈活和低功耗[4]。DSI協(xié)議架構(gòu)的最低層是物理層(Physical Layer,,PHY),,規(guī)范了發(fā)送端(主端)和接收端(從端)通道的電學(xué)特性和通道建立時的時序要求[5]D-PHY規(guī)范是一種常用的兼容DSI協(xié)議的物理層規(guī)范[6],。

    D-PHY一般包含一個時鐘通道,,一到四個數(shù)據(jù)通道,主要的工作模式有高速(High Speed,,HS)模式,、低功耗(Low-Power,LP)模式[7],。高速模式下,,D-PHY通道采用差分點(diǎn)對點(diǎn)傳輸,提供源同步時鐘,,數(shù)據(jù)傳輸采用突發(fā)式(Burst)傳輸,單通道數(shù)據(jù)傳輸速率最高支持1.5 Gb/s(D-PHY v1.1規(guī)范),,主要用于傳輸高速的圖像,、視頻數(shù)據(jù)流。低功耗模式下,,D-PHY只有通道0工作,,通道無端接,數(shù)據(jù)傳輸?shù)退偾铱砷g斷,,是一種異步通信模式[8],,通道數(shù)據(jù)傳輸速率最高支持10 Mb/s(D-PHY v1.1規(guī)范),主要用于傳輸控制和狀態(tài)信號事務(wù),。




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作者信息:

張自豪1,2,趙建中1,,周玉梅1,,2

(1.中國科學(xué)院微電子研究所,北京100029,;2.中國科學(xué)院大學(xué),,北京100049)




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