中圖分類號： TN402 文獻(xiàn)標(biāo)識碼： A DOI：10.16157/j.issn.0258-7998.212337 中文引用格式： 劉森態(tài)，龐宇,，魏東. 基于UVM的Wishbone-SPI驗(yàn)證平臺設(shè)計[J].電子技術(shù)應(yīng)用,，2022，48(6)：36-41. 英文引用格式： Liu Sentai,，Pang Yu,，Wei Dong. Design of Wishbone-SPI verification platform based on UVM[J]. Application of Electronic Technique，2022,，48(6)：36-41.
Design of Wishbone-SPI verification platform based on UVM
Liu Sentai,，Pang Yu，Wei Dong
Chongqing University of Posts and Telecommunications,，Chongqing 400065,，China
Abstract： As the complexity of the chip increases, the time it takes to verify the chip in the design process continues to increase. Aiming at the poor reusability and low coverage of traditional verification platforms, this paper uses Universal Verification Methodology(UVM) to design the Wishbone-SPI verification platform, uses UVM components to flexibly build the verification platform, completes the standard verification framework, and designs constrained random stimulus, automatically counting function coverage. The simulation results show that the functional coverage of the verification platform reaches 100%, and shows that the platform has good configurability and reusability.
Key words : UVM；SPI,；Wishbone,；verification platform
