中圖分類號： TP391
文獻標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.200532
中文引用格式： 任靜，李菁菁,，劉云飛. 基于FPGA的圖像壓縮編解碼系統(tǒng)設(shè)計[J].電子技術(shù)應(yīng)用,，2020，46(12)：111-115.
英文引用格式： Ren Jing,，Li Jingjing,，Liu Yunfei. Image compression coding and decoding system based on FPGA[J]. Application of Electronic Technique，2020,，46(12)：111-115.

Image compression coding and decoding system based on FPGA

Abstract： Aiming to real-time requirement of image processing, an image compression coding and decoding system based on FPGA is designed. The system includes real-time image acquisition, JPEG compression and UART transmission. The D5M camera is configured by Verilog hardware description language to acquire image. We focus on improving two-dimension discrete cosine transformation(2D-DCT) design flow in the image compression module. The dual frequency signal controller is adopted to reduce the call of adder based on the Chen algorithm and realize its fast operation. The test shows that the compression ratio of the image is 26.3:1, and the average signal-to-noise ratio is more than 40 dB. The visual effect of the compressed image is good, which meets the design requirements.

Key words : FPGA,；JPEG compression algorithm,；RS_232；D5M camera