基于FPGA的LVDS無時鐘數(shù)據(jù)傳輸方案設(shè)計與實現(xiàn)
2021年電子技術(shù)應(yīng)用第6期
畢彥峰1,李 杰1,,胡陳君2
1.中北大學(xué) 電子測試技術(shù)重點實驗室,,山西 太原030051; 2.蘇州中盛納米科技有限公司,,江蘇 蘇州215123
摘要: 針對離線式彈載數(shù)據(jù)采集存儲設(shè)備小型化需求,,設(shè)計了一種基于FPGA的LVDS(Low-Voltage Differential Signaling)無時鐘高速數(shù)據(jù)傳輸系統(tǒng)。在不外掛接口芯片的情況下,,用板載時鐘代替差分時鐘,,僅使用一對差分管腳即可完成一路LVDS無時鐘數(shù)據(jù)傳輸,系統(tǒng)中數(shù)據(jù)接口較多時可以很大程度上減少板卡體積,。通過提高FPGA內(nèi)部SERDES(Serializer-Deserializer)反串行化比例以及數(shù)據(jù)進(jìn)行8B/10B編碼解決鑒相器失效的問題,,并以此為板載時鐘提供準(zhǔn)確的相位信息來對齊串行數(shù)據(jù)和模擬時鐘,最后按照模擬時鐘將串行LVDS數(shù)據(jù)反序列化,,從而達(dá)到板載時鐘代替LVDS隨路時鐘的目的,,以此實現(xiàn)基于FPGA無隨路時鐘的LVDS高速傳輸。試驗表明,,該系統(tǒng)能夠可靠,、有效工作,具備一定工程實用價值,。
中圖分類號: TN919,;TP274
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.201076
中文引用格式: 畢彥峰,李杰,,胡陳君. 基于FPGA的LVDS無時鐘數(shù)據(jù)傳輸方案設(shè)計與實現(xiàn)[J].電子技術(shù)應(yīng)用,,2021,47(6):62-66.
英文引用格式: Bi Yanfeng,,Li Jie,,Hu Chenjun. Design and implementation of LVDS clockless data transmission scheme based on FPGA[J]. Application of Electronic Technique,2021,,47(6):62-66.
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.201076
中文引用格式: 畢彥峰,李杰,,胡陳君. 基于FPGA的LVDS無時鐘數(shù)據(jù)傳輸方案設(shè)計與實現(xiàn)[J].電子技術(shù)應(yīng)用,,2021,47(6):62-66.
英文引用格式: Bi Yanfeng,,Li Jie,,Hu Chenjun. Design and implementation of LVDS clockless data transmission scheme based on FPGA[J]. Application of Electronic Technique,2021,,47(6):62-66.
Design and implementation of LVDS clockless data transmission scheme based on FPGA
Bi Yanfeng1,,Li Jie1,Hu Chenjun2
1.State Key Laboratory of Electronic Testing Technology,,North University of China,,Taiyuan 030051,China,; 2.Suzhou Zhongsheng Nanotechnology Company,,Suzhou 215123,China
Abstract: Aiming at the miniaturization requirements of off-line bomb-borne data acquisition and storage equipment, an FPGA-based LVDS clockless high-speed data transmission system is designed. Without an external interface chip, the onboard clock is used to replace the differential clock, and only a pair of differential pins can complete a LVDS clockless data transmission. When there are many data interfaces in the system, the board volume can be greatly reduced. The problem of phase detector failure is solved by increasing the deserialization ratio of the FPGA internal SERDES and 8B/10B encoding of the data, so to provide accurate phase information for the onboard clock to align the serial data and the analog clock. Finally,,following the analog clock,,the serial LVDS data is deserialized, so as to achieve the purpose of replacing the LVDS accompanying clock with the onboard clock, so as to achieve high-speed LVDS transmission based on FPGA without accompanying clock. Tests show that the system can work reliably and effectively, and has certain engineering practical value.
Key words : FPGA;no clock transmission,;LVDS,;SERDES
0 引言
常規(guī)彈藥制導(dǎo)化改造試驗過程中,事后回讀彈載數(shù)據(jù)記錄儀所記錄的各種指令參數(shù)是測試反饋中重要的方式,。在靶場測設(shè)發(fā)射導(dǎo)彈之前,,數(shù)據(jù)回讀也是監(jiān)測彈藥狀態(tài)的一種十分重要的方式,。隨著科技的進(jìn)步,數(shù)據(jù)存儲設(shè)備愈發(fā)趨近小型化,、高速化,,所能提供的數(shù)據(jù)回讀接口也越來越少,,導(dǎo)致對采集存儲設(shè)備進(jìn)行數(shù)據(jù)回讀時無法同時滿足速度快和接口少的條件[1-2],。
本文詳細(xì)內(nèi)容請下載:http://forexkbc.com/resource/share/2000003575。
作者信息:
畢彥峰1,,李 杰1,,胡陳君2
(1.中北大學(xué) 電子測試技術(shù)重點實驗室,山西 太原030051,;
2.蘇州中盛納米科技有限公司,,江蘇 蘇州215123)
此內(nèi)容為AET網(wǎng)站原創(chuàng),未經(jīng)授權(quán)禁止轉(zhuǎn)載,。