中圖分類號： TN405.97 文獻(xiàn)標(biāo)識碼： A DOI：10.16157/j.issn.0258-7998.211370 中文引用格式： 王夢雅,，曾燕萍，張景輝,，等. 基于SiP封裝的DDR3時(shí)序仿真分析與優(yōu)化[J].電子技術(shù)應(yīng)用,，2021，47(10)：42-47. 英文引用格式： Wang Mengya,，Zeng Yanping,，Zhang Jinghui，et al. Timing simulation analysis and optimization of DDR3 based on SiP package[J]. Application of Electronic Technique,，2021,，47(10)：42-47.
Timing simulation analysis and optimization of DDR3 based on SiP package
Wang Mengya，Zeng Yanping，Zhang Jinghui,，Zhou Qianrong
China Electronic Technology Group Corporation No.58 Research Institute,，Wuxi 214035，China
Abstract： Aiming at the timing requirements of DDR3 system, timing simulation and optimization were carried out for DDR3 package and substrate design in a SiP(System in Package). Through simulation guidance design, the design success rate of DDR3 in SiP product was improved and the design cycle was reduced. The signal scattering parameters were extracted by ANSYS SIwave software, and then the topology construction and timing simulation analysis was carried out through Cadence SystemSI software. The relationship between signal timing and waveform was discussed based on the theory of signal integrity. The actual optimization scheme was given by combining with layout analysis. Finally, the designed DDR3 system could meet the timing requirements of JEDEC protocol through simulation iteration verification.
Key words : DDR3,；SiP(system in package),；timing simulation；high density interconnection,；signal integrity
0 引言
系統(tǒng)級封裝(System in Package,，SiP)是利用先進(jìn)封裝技術(shù)將不同功能的芯片集成在一個(gè)微系統(tǒng)內(nèi)，具備小型化,、低功耗和高性能等優(yōu)勢,，已成為半導(dǎo)體行業(yè)關(guān)注的重要焦點(diǎn)之一[1-4]。SiP中經(jīng)常集成高頻率高帶寬的DDR3系統(tǒng)來實(shí)現(xiàn)存儲(chǔ)功能,，但是與傳統(tǒng)PCB不同,，基于SiP封裝的高密度互聯(lián)DDR3的復(fù)雜性設(shè)計(jì)帶來的信號完整性問題日益嚴(yán)重[5-8]。除了單純從信號的眼圖和波形來判斷信號質(zhì)量外,，DDR3的設(shè)計(jì)還面臨著嚴(yán)格的時(shí)序要求,，即使信號波形達(dá)到JEDEC協(xié)議中規(guī)定的判決標(biāo)準(zhǔn)，數(shù)據(jù)與選通信號,、地址與時(shí)鐘信號等之間的時(shí)延也不一定符合協(xié)議規(guī)范,，DDR3的接口時(shí)序分析成為DDR3設(shè)計(jì)的重中之重[9-10]。
