中圖分類號： TN955+.3 文獻標(biāo)識碼： A DOI：10.16157/j.issn.0258-7998.211901 中文引用格式： 汪敏,，蔣彥雯，范紅旗. 基于虛擬儀器的DRFM干擾模擬器設(shè)計[J].電子技術(shù)應(yīng)用,，2022,，48(3)：118-122，128. 英文引用格式： Wang Min,，Jiang Yanwen,，F(xiàn)an Hongqi. Design of DRFM jamming simulator using virtual instrument[J]. Application of Electronic Technique，2022,，48(3)：118-122,，128.
Design of DRFM jamming simulator using virtual instrument
Wang Min1,，2,，Jiang Yanwen1，F(xiàn)an Hongqi1
1.National Key Laboratory of Science and Technology on Automatic Target Recognition,， National University of Defense Technology,，Changsha 410000，China,； 2.Unit 94535 of PLA,，Xuzhou 221000，China
Abstract： In order to meet the technical verification and system testing requirements of radar countermeasures against digital radio frequency memory(DRFM) jamming, a modular, scalable, lightweight and portable vector signal transceiver combined with DRFM technology is designed. The simulator control part adopts a kind of flow controller to realize, and the effectiveness of the design is verified by the injection test of the radar and jamming simulator. This design can generate various types of radar jamming signals, including interrupted-sampling and repeater jamming according to the radar echo. It can realize multiple mission functions by replacing and expanding the board. It can be used in the construction of radar test environment to support the research and verification of radar anti-jamming technology.
Key words : jamming simulation,；DRFM,；virtual instrument；interrupted-sampling,；FPGA
0 引言
作為現(xiàn)代電子對抗中的核心技術(shù),，數(shù)字射頻存儲(Digital Radio Frequency Memory，DRFM)干擾技術(shù)以其調(diào)制方式的靈活性,、信號相干性等特點,，廣泛應(yīng)用于各類自衛(wèi)式、支援式和投擲式干擾系統(tǒng)中[1],。對抗DRFM干擾,、尤其是來自雷達主瓣的DRFM干擾[2]，成為了當(dāng)前各類雷達研制測試中的一項重要課題,，因此研制一種能滿足技術(shù)驗證與系統(tǒng)測試需求的DRFM干擾模擬器就顯得尤為必要,。
