中圖分類號(hào)： TN919 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.222620 中文引用格式： 趙世超，左金印,，魏驍,，等. 基于FPGA的萬兆以太網(wǎng)UDP協(xié)議通信接口設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2022,，48(10)：113-117,，122. 英文引用格式： Zhao Shichao，Zuo Jinyin,，Wei Xiao,，et al. Design of 10 gigabit ethernet UDP communication module based on FPGA[J]. Application of Electronic Technique,，2022，48(10)：113-117,，122.
Design of 10 gigabit ethernet UDP communication module based on FPGA
Zhao Shichao,，Zuo Jinyin，Wei Xiao,，Zhao Zhe
National Computer System Engineering Research Institute of China,，Beijing 100083，China
Abstract： In order to solve the rapidly growing data transmission problem for embedded devices, this paper introduces a 10 gigabit UDP/IP protocol communication module, which relies on the Field Programmable Gate Array(FPGA) platform and uses optical fiber as the transmission medium,，and explores the impact of introducing the branch prediction mechanism on the transmission delay of the communication interface module. Through in-depth research on the typical transmission model of the existing Open Systems Interconnection(OSI),，using hardware description language, the ARP controller, IP controller and UDP controller are modularly designed to form a complete UDP/IP communication module. And the influence of introducing the branch prediction mechanism on the transmission delay of the communication module is evaluated. The analysis shows that the design is simple to implement and adapts to the requirements of embedded devices for high bandwidth, low latency and low resource occupation. It maintains the ARP table independently and supports multi-device cascading. It has positive significance in application scenarios such as high-speed data acquisition, long-distance information transmission, and high-speed processing of on-chip data.
Key words : FPGA；fiber-optic communication,；10 gigabit ethernet,；UDP/IP protocol；branch prediction
