中圖分類(lèi)號(hào)：TN401 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.223026 中文引用格式： 鄧佳偉,，王琪,，張梅娟，等. 多態(tài)性PCIE橋擴(kuò)展芯片的設(shè)計(jì)和硅后驗(yàn)證[J]. 電子技術(shù)應(yīng)用,，2023,，49(2)：20-25. 英文引用格式： Deng Jiawei，Wang Qi,，Zhang Meijuan,，et al. Design and post-silicon verification of polymorphic PCIE bridge expansion chip[J]. Application of Electronic Technique，2023,，49(2)：20-25.
Design and post-silicon verification of polymorphic PCIE bridge expansion chip
Deng Jiawei,，Wang Qi，Zhang Meijuan,，Zhang Mingyue,，Yang Chuwei
The No.58 Research Institute of China Electronics Technology Group Corporation， Wuxi 214060,， China
Abstract： As a mainstream bus protocol, the application scenarios of PCIE(Peripheral Component Interconnect Express) bus are more and more abundant, and the peripheral devices connected on the bus are also increasing. On both desktop and embedded general-purpose processors, the number of PCIE controllers is limited, and the functions of many PCIE bridge chips are also very limited. A polymorphic PCIE expansion bridge chip is designed to extend the processor's processing capability. The chip's multi-channel, high-throughput, polymorphic attributes effectively make up for the shortcomings of the traditional PCIE processor. The scheme determines the feasibility and the stability of the chip through the post-silicon verification method, and also provides a designed idea suitable for the follow-up PCIE extended chip.
Key words : PCIE bridge,；functional verification；polymorphism,；chip,；chip design
