《電子技術(shù)應(yīng)用》
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PCIe總線DMA高速傳輸系統(tǒng)的設(shè)計與實(shí)現(xiàn)
電子技術(shù)應(yīng)用
劉佳寧,,單偉,劉金鵬
中國電子科技集團(tuán)公司第五十八研究所,,江蘇 無錫 214035
摘要: 針對數(shù)據(jù)傳輸系統(tǒng)中外設(shè)帶寬受限,、有效帶寬低的問題,設(shè)計了一種PCIe總線的DMA高速傳輸系統(tǒng),。以FPGA為控制核心,,采用PIO操作與DMA操作分時組合的控制模式實(shí)現(xiàn)全雙工DMA讀寫通道的傳輸層協(xié)議。PIO操作配合中斷實(shí)現(xiàn)指令與狀態(tài)實(shí)時收發(fā),,DMA模塊設(shè)計了一種兩段式切片的裁剪機(jī)制實(shí)現(xiàn)PCIe協(xié)議的傳輸長度控制,,發(fā)送模塊設(shè)計請求仲裁邏輯實(shí)現(xiàn)請求事務(wù)的優(yōu)先級仲裁,接收模塊采用本地緩存TAG標(biāo)號的方法實(shí)現(xiàn)請求回應(yīng)的實(shí)時管理并解決回應(yīng)亂序問題。最后通過時鐘計數(shù)的方法測試傳輸速度,,分析了影響讀寫傳輸速度的制約因素,。經(jīng)驗(yàn)證,DMA寫操作有效帶寬已經(jīng)達(dá)到75%,,非常接近80%的理論極限,,DMA讀操作也達(dá)到了60%。本設(shè)計解決了高速數(shù)據(jù)傳輸系統(tǒng)中的帶受限寬問題,,具有一定的工程應(yīng)用價值,。
中圖分類號:TP393 文獻(xiàn)標(biāo)志碼:A DOI: 10.16157/j.issn.0258-7998.233808
中文引用格式: 劉佳寧,單偉,,劉金鵬. PCIe總線DMA高速傳輸系統(tǒng)的設(shè)計與實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用,,2023,49(12):85-89.
英文引用格式: Liu Jianing,,Shan Wei,,Liu Jinpeng. Design and implementation of DMA high-speed transmission system based on PCIe[J]. Application of Electronic Technique,2023,,49(12):85-89.
Design and implementation of DMA high-speed transmission system based on PCIe
Liu Jianing,Shan Wei,,Liu Jinpeng
China Electronics Technology Group Corporation 58th Research Institute,, Wuxi 214035, China
Abstract: According to the issue of limited and low-effective peripheral bandwidth in transmission system, this paper designs a DMA high-speed transmission system based on PCIe. Taking FPGA as control unit, the transaction layer protocol of full duplex DMA read and write channels is realized with the time-sharing control method which combined PIO and DMA. Then PIO receives the instructions and translates real-time status information, DMA controller takes charge of the transfer size with a two-section-slice clipping mechanism, transmit engine arbitrates all of the requests according to the priority logic, receive engine performs real-time management of completion packet by caching the TAG label, and solves out-of-order problem. At last, the transmission speed is tasted by means of clock counter,, and the restriction factors affecting read/write transmission speed are analyzed. By the practical verification, the effective bandwidth of DMA write has reached 75%, which is very close to the theoretical limit of 80%, and DMA read effective bandwidth has also reached 60%. The design solved the problem of bandwidth limitation in high-speed transmission system, and affords certain engineering application value.
Key words : PCIe bus,;DMA;two-section slice,;request arbitration,;out-of-order

0 引言

隨著信息技術(shù)的不斷發(fā)展,通信系統(tǒng)對數(shù)據(jù)傳輸帶寬的要求也越來越高,。作為系統(tǒng)內(nèi)部數(shù)據(jù)交互的橋梁,,IO總線是決定整個系統(tǒng)傳輸帶寬和處理性能的關(guān)鍵[1]。

傳統(tǒng)的第二代IO總線以PCI和PCI-X總線為代表,,其特點(diǎn)是時鐘頻率較低,,數(shù)據(jù)總線并行傳輸,在傳輸速度和硬件成本等方面制約了PCI總線的整體帶寬[2],,且由于總線共享,,單一外設(shè)無法長時間占用總線,進(jìn)一步限制了總的傳輸速率[3],。新興的第三代IO總線PCI Express(PCIe)總線解決了上述問題,。PCIe總線采用點(diǎn)到點(diǎn)串行差分結(jié)構(gòu),所有外設(shè)設(shè)備通過獨(dú)立通道實(shí)現(xiàn)互聯(lián)[4],因此所有外設(shè)單獨(dú)使用總線通道的所有帶寬,,且各設(shè)備間可以并發(fā)傳輸互不影響[5],,因此系統(tǒng)的整體性能得到有效提升,解決了高速數(shù)據(jù)傳輸?shù)耐掏铝繂栴},。在現(xiàn)代通信領(lǐng)域,,PCIe總線的使用前景十分廣闊。

本文設(shè)計了一種基于PCIe總線架構(gòu)的高速數(shù)據(jù)傳輸系統(tǒng),,考慮到PCIe協(xié)議的復(fù)雜性,,可以使用協(xié)議芯片簡化設(shè)計[6],本文則使用Xilinx官方提供的軟核作為PHY模塊實(shí)現(xiàn)PCIe鏈路層協(xié)議,,同時利用FPGA豐富的邏輯資源和緩存資源設(shè)計頂層應(yīng)用模塊,,完成PCIe協(xié)議包的收發(fā),實(shí)現(xiàn) PCIe板卡的完整協(xié)議,。最后聯(lián)合上層軟件控制程序和底層驅(qū)動構(gòu)成完整的閉環(huán)傳輸測試系統(tǒng),,為同類型數(shù)據(jù)傳輸系統(tǒng)的工程應(yīng)用提供了設(shè)計參考。


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作者信息:

劉佳寧,,單偉,,劉金鵬

(中國電子科技集團(tuán)公司第五十八研究所,江蘇 無錫 214035)





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