《電子技術(shù)應(yīng)用》
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應(yīng)用于收發(fā)鏈路多模塊級聯(lián)的優(yōu)化設(shè)計方法
電子技術(shù)應(yīng)用
余秋實,,郭潤楠,,陳昊,莊園,,梁云,,閆昱君,吳霞,,葛逢春,,王維波,,陶洪琪
南京電子器件研究所 固態(tài)微波器件與電路全國重點實驗室
摘要: 為解決波束賦形芯片中子電路模塊由于寄生效應(yīng)而導(dǎo)致的級聯(lián)失配問題提出了一種優(yōu)化設(shè)計方法。該設(shè)計方法通過主動引入相鄰器件阻抗?fàn)恳?yīng),,并使其與級聯(lián)阻抗失配相抵消從而實現(xiàn)阻抗“預(yù)失配”的設(shè)計方案,。對“預(yù)失配”的技術(shù)原理以及設(shè)計流程進行了簡要分析,并通過加工一款采用優(yōu)化設(shè)計方案的4通道X/Ku波段的射頻收發(fā)芯片,,驗證了該設(shè)計方案的可實現(xiàn)性與有效性。在8 GHz~18 GHz頻帶范圍內(nèi),,該芯片與基于端口駐波設(shè)計體系的原芯片相比,,收發(fā)鏈路增益分別為6.5 dB和14 dB,提升了超過2 dB,。發(fā)射鏈路輸出功率21 dBm,,發(fā)射效率為15.7%,分別提升了1 dB和9%,。接收鏈路噪聲系數(shù)為8.72 dB,,降低了1.2 dB。收發(fā)鏈路最大移相均方根誤差為5.12°和5.25°,,分別下降了3.17°和1.75°,。
中圖分類號:TN454 文獻標志碼:A DOI: 10.16157/j.issn.0258-7998.244892
中文引用格式: 余秋實,郭潤楠,,陳昊,,等. 應(yīng)用于收發(fā)鏈路多模塊級聯(lián)的優(yōu)化設(shè)計方法[J]. 電子技術(shù)應(yīng)用,2024,,50(5):77-83.
英文引用格式: Yu Qiushi,,Guo Runnan,Chen Hao,,et al. An optimization design scheme applied to multi-modules cascading of transceiver IC[J]. Application of Electronic Technique,,2024,50(5):77-83.
An optimization design scheme applied to multi-modules cascading of transceiver IC
Yu Qiushi,,Guo Runnan,,Chen Hao,Zhuang Yuan,,Liang Yun,,Yan Yujun,Wu Xia,,Ge Fengchun,, Wang Weibo,Tao Hongqi
National Key Laboratory of Solid-state Microwave Devices and Circuits,,Nanjing Electronic Devices Institute
Abstract: In this paper, a novel optimization design scheme is proposed to solve the cascading mismatch problem of sub-circuits in beamforming chips due to parasitic effects. The optimization design scheme proposed in this paper is a design scheme that realizes impedance “pre-mismatch” by introducing the impedance traction effect of adjacent modules and offsetting it with the cascade impedance mismatch. The theory of the “pre-mismatch” technique is provided in the article and a 4-channel X/Ku-band RF transceiver chip has been fabricated to verify the feasibility and effectiveness of this scheme. Compared to conventional designs, the chip operates within the frequency band of 8 GHz~18 GHz, with the receive and transmit average link gains of 6.5 dB and 14 dB, respectively. Both transceiver link gains are increased by more than 2 dB. The transmit link output power is 21 dBm and power-added efficiency is 15.7%,,optimized by 1 dB and 9%. The receive link noise figure of 8.72 dB is reduced by 1.2 dB. The maximum phase-shifted root-means-square errors of the transceiver link are 5.25°and 5.12°, with a decrease of 1.75° and 3.17°.
Key words : multi-modules cascading,;X/Ku-band;GaAs pHEMT,;Monolithic Microwave Integrated Circuit (MMIC),;phased array transceiver

引言

隨著電子信息技術(shù)不斷發(fā)展,越來越多的電子設(shè)備終端采用了相控陣體制,。作為相控陣系統(tǒng)中的關(guān)鍵器件,,波束賦形芯片通常由包括放大器、移相器,、衰減器等子電路模塊組成[1],。傳統(tǒng)設(shè)計中為了簡化級聯(lián)設(shè)計,這些子電路模塊端口通常都被匹配至標準50 Ω負載,。然而由于寄生效應(yīng)的存在使得子電路模塊端口阻抗往往不能完美匹配到50 Ω[2],,特別是在一些寬帶應(yīng)用場景中。這種非完美的阻抗匹配會使得各子電路模塊間產(chǎn)生失配,,導(dǎo)致鏈路性能的下降,。因此,如何減少模塊間級聯(lián)失配導(dǎo)致的性能下降成為熱門研究課題,。

在傳統(tǒng)收發(fā)組件的設(shè)計中,,為了盡可能減少失配問題,針對單個子電路模塊提出了多種優(yōu)化方案,,包括采用算法優(yōu)化匹配技術(shù)[3],、多頻選擇寬帶匹配技術(shù)[4],以及針對多態(tài)器件的優(yōu)化單元排序[5]和單元低插損設(shè)計方法[6],。通過上述設(shè)計方法,,可以有效降低單個子電路模塊的端口失配,但是這些設(shè)計方案僅僅聚焦于單個子電路模塊,。在收發(fā)組件中,,由于多個子電路模塊在級聯(lián)時會產(chǎn)生阻抗?fàn)恳沟媚K之間相互影響,。即便經(jīng)過了上述的單模塊優(yōu)化方案,,隨著級聯(lián)的模塊越來越多,各模塊端口的失配誤差也會在鏈路中不斷積累,,最終導(dǎo)致鏈路性能進一步惡化[7],。因此在收發(fā)鏈路中的多模塊級聯(lián)設(shè)計時,需要采用一種全局性的阻抗匹配策略,。


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作者信息:

余秋實,,郭潤楠,陳昊,,莊園,,梁云,,閆昱君,吳霞,,葛逢春,,王維波,陶洪琪

(南京電子器件研究所 固態(tài)微波器件與電路全國重點實驗室,,江蘇 南京 210016)


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