中圖分類號(hào)：TN402 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.240803 中文引用格式： 徐加山,，姚舒雨,，徐志磊. 使用Cadence AI技術(shù)加速驗(yàn)證效率提升[J]. 電子技術(shù)應(yīng)用，2024,，50(8)：32-36. 英文引用格式： Xu Jiashan,，Yao Shuyu，Xu Zhilei. Accelerating verification efficiency with Cadence AI technology[J]. Application of Electronic Technique,，2024,，50(8)：32-36.
Accelerating verification efficiency with Cadence AI technology
Xu Jiashan1，Yao Shuyu1,，Xu Zhilei2
1.Shenzhen Sanechips Technology Co.,， Ltd.， China,；2.Cadence Design Systems,， Inc.
Abstract： With the increasing scale and complexity of hardware design, the verification convergence challenge is becoming more difficult. Simply increasing the number of CPU cores to increase parallel testing cannot solve this problem fundamentally. How to achieve verification convergence before tape-out is a difficult problem that verification engineers have to face. To solve this problem, this article proposes two efficiency improvement solutions: AI-driven verification EDA tools and large-scale model generation. The EDA tools include Cadence's AI-driven Verisium apps and Xcelium ML using machine learning technology. The former is used to improve the fault location efficiency of verification, including Verisium AutoTriage, Verisium SemanticDiff, and Verisium WaveMiner. The latter can be used to improve the verification coverage convergence efficiency. Large-scale model generation can assist intelligent debugging and automatically generate verification cases. This article mainly introduces each implementation solution and gives the project experimental improvement results.
Key words : IC verification；AI,；Verisium apps,；efficiency improvement
