中圖分類號： TN402
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.209801
中文引用格式： 邊少鮮,，Micheal Feng，David Yue,，等. Innovus機器學(xué)習(xí)在高性能CPU設(shè)計中的應(yīng)用[J].電子技術(shù)應(yīng)用,，2020，46(8)：54-59，63.
英文引用格式： Bian Shaoxian,，Micheal Feng,，David Yue，et al. Innovus machine learning application in performance CPU design[J]. Application of Electronic Technique,，2020,，46(8)：54-59，63.

Innovus machine learning application in performance CPU design

Abstract： The high-performance chip design has a larger design scale, higher frequency, more complex design data and reliability, and more signoff indicators under 7 nm and higher process nodes. Machine learning has been successfully applied in many fields, and complex chip design is a good field for applying machine learning. Cadence built the algorithm into the Innovus tool, and built the machine learning model by learning and modeling the chip design data to improve chip performance. A physical design process that applies machine learning to optimize latency is established to improve chip design performance. This paper presents a machining-learning-based physical design flow that optimizes delay to improve chip design performance. In orde to choose a better solution,，the effect of optimizing the cell delay,，net delay，cell and net delay separately on the design was discussed and analyisised in detail. Finally,，the solution is applied to another block design with more difficult design and higher performance requirements . To verifies the consistency of the flow,，a more comprehensive analysis is completed from the aspects of timing，power,，wire length,，etc.

Key words : machine learning；Innovus,；chip design,；physical design