Abstract： The high-performance chip design has a larger design scale, higher frequency, more complex design data and reliability, and more signoff indicators under 7 nm and higher process nodes. Machine learning has been successfully applied in many fields, and complex chip design is a good field for applying machine learning. Cadence built the algorithm into the Innovus tool, and built the machine learning model by learning and modeling the chip design data to improve chip performance. A physical design process that applies machine learning to optimize latency is established to improve chip design performance. This paper presents a machining-learning-based physical design flow that optimizes delay to improve chip design performance. In orde to choose a better solution,，the effect of optimizing the cell delay，net delay,，cell and net delay separately on the design was discussed and analyisised in detail. Finally,，the solution is applied to another block design with more difficult design and higher performance requirements . To verifies the consistency of the flow，a more comprehensive analysis is completed from the aspects of timing,，power,，wire length，etc.
Key words : machine learning,；Innovus,；chip design；physical design
0 引言
摩爾定律揭示了集成電路的集成度和技術(shù)節(jié)點(diǎn)的飛速發(fā)展,，這使得芯片設(shè)計(jì)的復(fù)雜度和數(shù)據(jù)量快速上升,，尤其是芯片的物理設(shè)計(jì)更是涉及海量的數(shù)據(jù)和信息，且運(yùn)行時(shí)間和設(shè)計(jì)周期漫長(zhǎng),，迭代一次的時(shí)間和資源代價(jià)很大,，這對(duì)設(shè)計(jì)師的經(jīng)驗(yàn)與能力要求很高。機(jī)器學(xué)習(xí)如今在各個(gè)領(lǐng)域都有廣泛的應(yīng)用,，其能學(xué)習(xí)數(shù)據(jù)規(guī)律建立模型從而快速推斷結(jié)果[1],。如果能在物理設(shè)計(jì)中應(yīng)用機(jī)器學(xué)習(xí)挖掘設(shè)計(jì)規(guī)律，且基于推斷的求解來(lái)進(jìn)行物理設(shè)計(jì),，可加速芯片設(shè)計(jì),。國(guó)內(nèi)外很多學(xué)者在此方面有了成功的研究，包括PAN D Z等詳細(xì)介紹的在物理設(shè)計(jì)中應(yīng)用機(jī)器學(xué)習(xí)[2],。LI B使用機(jī)器學(xué)習(xí)由全局布線(xiàn)線(xiàn)預(yù)測(cè)詳細(xì)布線(xiàn)結(jié)果[3],。TSMC在物理設(shè)計(jì)中應(yīng)用機(jī)器學(xué)習(xí)的兩款芯片分別可使頻率提升40 MHz和減少20 000時(shí)鐘門(mén)控單元等[4]。
