A 20 MS/s second-order noise shaping SAR ADC with VCO-based comparator
Wang Ye1,，2,，Liu Liyuan2，3,，Wu Nanjian2,，3
(1.School of Microelectronics，University of Science and Technology of China,，Hefei 230026,，China； 2.Institute of Semiconductors,，Chinese Academy of Sciences,，Beijing 100083，China,； 3.State Key Laboratory of Superlattices and Microstructures,，Beijing 100083，China)
Abstract： A second-order noise-shaping successive approximation register(NS-SAR) analog-to-digital converter(ADC) with a voltage-controlled oscillator(VCO)-based comparator is presented in this paper. Firstly, a VCO-based comparator with low voltage sensitivity and better noise performance is adopted. Then the zero pole of the noise transfer function is optimized by the dynamic amplifier. Finally, the noise in the signal band is suppressed by the noise shaping structure. A design example of 12 bit 20 MS/s NS-SAR ADC was fabricated in a 180 nm CMOS technology. Simulation results show that, it consumes 1.12 mW at a 1.3 V power supply and achieves a FoMs of 163 dB with 72.7 dB SNDR, 88 dB SFDR at an oversampling ratio(OSR) of 8, and the effective number of bits(ENOB)>11.7 bit in the supply voltage range of 1.3～1.8 V.
Key words : ADC,；noise-shaping,；VCO-based comparator；dynamic amplifier
