中圖分類號(hào)： TN402 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.219801 中文引用格式： 萬健,，王碩，邱歡,，等. 基于Innovus工具的IR Drop自動(dòng)化修復(fù)[J].電子技術(shù)應(yīng)用,，2021，47(8)：43-47. 英文引用格式： Wan Jian,，Wang Shuo,，Qiu Huan，et al. Automatic IR drop fixing with Innovus implementation system[J]. Application of Electronic Technique,，2021,，47(8)：43-47.
Automatic IR drop fixing with Innovus implementation system
Wan Jian1，Wang Shuo1,，Qiu Huan1,，Chen Feiyang1，Ye Lin1，Wu Chenfei1,，2,，Ouyang Keqing1，2
1.Department of Back-End Design,，Sanechips Technology Co.,，Ltd.，Shenzhen 518055,，China,； 2.State Key Laboratory of Mobile Network and Mobile Multimedia Technology,，Shenzhen 518055,，China
Abstract： At the advanced process nodes, due to resistive power grid and simultaneous switching of close instances, there is a voltage reduction(IR drop) on VDD nets and an increase on VSS nets. IR drop may cause timing issues and functional failures of chips. In this paper, three automatic IR drop fixing flows based on Innovus implementation system were used to avoid and fix the possible dynamic IR drop issues during the PR(Placement and Route) stage. The results show that the Pegasus PG fix flow and IR-Aware placement flow could reduce the IR drop violations of 48.0% and 33.8% respectively, and would not deteriorate the timing and DRC(Design Rule Check). However, the optimization effect of IR drop issues was relatively small with IR-Aware PG strape addition flow and DRC greatly deteriorated.
Key words : chip design；Innovus implementation system,；IR drop fixing
0 引言
在先進(jìn)工藝節(jié)點(diǎn)下,，芯片集成度極大提高，電源網(wǎng)絡(luò)的電阻增加和高密度的晶體管(可稱為Cell)同時(shí)翻轉(zhuǎn)會(huì)在供電線(Power nets and Ground nets,，簡(jiǎn)稱PG)上產(chǎn)生IR Drop[1-4],。先進(jìn)工藝下，5%～10%的IR Drop可能會(huì)引起時(shí)序問題,，20%～30%的IR Drop可能會(huì)導(dǎo)致功能性障礙,，因此在芯片設(shè)計(jì)過程中，IR Drop的預(yù)防和優(yōu)化也就顯得越來越重要,。
