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高吞吐率低時(shí)延圖像DCT處理器設(shè)計(jì)
2021年電子技術(shù)應(yīng)用第9期
劉思軍1,2,,秦明偉1,,劉多強(qiáng)1,,2
1.西南科技大學(xué) 信息工程學(xué)院,,四川 綿陽621010;2.中國直升機(jī)設(shè)計(jì)研究所,,江西 景德鎮(zhèn)333000
摘要: 針對(duì)高分辨率,、高幀率圖像實(shí)時(shí)壓縮問題,設(shè)計(jì)了一種應(yīng)用于高速圖像JPEG壓縮編碼系統(tǒng)的離散余弦變換(DCT)處理器,。設(shè)計(jì)的DCT處理器基于Virtex-7系列FPGA,,充分利用并行和流水線處理技術(shù),采用基于蝶形流圖結(jié)構(gòu)的行列分解算法,,實(shí)現(xiàn)了快速二維離散余弦變換(2D-DCT),。為了提高數(shù)據(jù)吞吐率,設(shè)計(jì)了雙核DCT處理單元,,可同時(shí)處理16個(gè)像素,,從整體上提高處理速度和降低時(shí)延。板級(jí)測(cè)試表明,,高速圖像DCT處理器數(shù)據(jù)計(jì)算結(jié)果正確,,在200 MHz系統(tǒng)時(shí)鐘下,吞吐率高達(dá)3 GB/s,,此時(shí)平均每幀圖像處理時(shí)間不超過10 ms,,實(shí)現(xiàn)了高速圖像的實(shí)時(shí)處理。
中圖分類號(hào): TN911,;TP335
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.200814
中文引用格式: 劉思軍,,秦明偉,劉多強(qiáng). 高吞吐率低時(shí)延圖像DCT處理器設(shè)計(jì)[J].電子技術(shù)應(yīng)用,,2021,,47(9):69-74.
英文引用格式: Liu Sijun,Qin Mingwei,,Liu Duoqiang. Design of high throughput rate low latency image DCT processor[J]. Application of Electronic Technique,,2021,47(9):69-74.
Design of high throughput rate low latency image DCT processor
Liu Sijun1,,2,,Qin Mingwei1,Liu Duoqiang1,,2
1.School of Information Engineering,Southwest University of Science and Technology,,Mianyang 621010,,China; 2.China Helicopter Design and Research Institute,Jingdezhen 333000,,China
Abstract: Aiming at the high-resolution and high-frame rate image real-time compression problem, a discrete cosine transform processor for high-speed image JPEG compression coding system was designed. The designed discrete cosine transform(DCT) processor is based on the Virtex-7 series FPGA, which makes full use of parallel and pipeline processing technology, and implements a fast two-dimensional discrete cosine transform(2D-DCT) by using a matrix-like decomposition algorithm based on the butterfly flow graph structure. In order to improve the data throughput rate, a dual-core DCT unit is designed to process 16 pixels at the same time, which improves the processing speed and reduces the delay as a whole. The board test shows that the calculation results of high-speed image DCT processor are correct. Under the 200 MHz system clock, the throughput rate is up to 3 GB/s, and the average image processing time per frame is no more than 10 ms, realizing the real-time processing of high-speed images.
Key words : image compression,;discrete cosine transform(DCT);FPGA,;parallel pipeline structure,;high throughput

0 引言

    DCT變換運(yùn)算量大,是圖像處理中計(jì)算復(fù)雜,、耗時(shí)長的運(yùn)算單元,。目前學(xué)界提出了兩種快速DCT變換算法:一類是尋求類似于FFT的蝶形算法來計(jì)算DCT[1],另一類是根據(jù)DCT變換的規(guī)律尋求快速算法[2],。在第二類算法中,,最常用的快速算法是行列分解法,該算法最初由Chen等人提出[3],。典型的圖像DCT處理器的輸入端采用串行輸入機(jī)制,,在進(jìn)行DCT變換前進(jìn)行串并轉(zhuǎn)換[4],吞吐率不高,,耗時(shí)長,,實(shí)時(shí)性差,無法應(yīng)用于高分辨率,、高幀率視覺測(cè)量場(chǎng)景,。

    針對(duì)高速大容量圖象的處理,馬林[5]等人針對(duì)2 048×2 048像素,、幀頻為150 f/s的高速圖像數(shù)據(jù)設(shè)計(jì)了存儲(chǔ)與實(shí)時(shí)顯示系統(tǒng),,便于延長記錄時(shí)間和顯示;楊志勇[6]等人針對(duì)星載圖像高速大容量存儲(chǔ)的文件化壞塊管理進(jìn)行了設(shè)計(jì),。本文從圖像壓縮變換角度延長記錄時(shí)間和節(jié)省數(shù)據(jù)存儲(chǔ)空間,,針對(duì)高速風(fēng)洞試驗(yàn)中視覺測(cè)量設(shè)備產(chǎn)生的分辨率可達(dá)5 120像素×5 120像素、幀率達(dá)80 f/s以上的高分辨率,、高幀率海量圖像數(shù)據(jù)的實(shí)時(shí)壓縮問題,,研究設(shè)計(jì)了一種應(yīng)用于高速圖像JPEG壓縮編碼的高吞吐率、低延時(shí)的DCT處理器,。




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作者信息:

劉思軍1,2,,秦明偉1,,劉多強(qiáng)1,2

(1.西南科技大學(xué) 信息工程學(xué)院,,四川 綿陽621010,;2.中國直升機(jī)設(shè)計(jì)研究所,,江西 景德鎮(zhèn)333000)




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