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DMSA在時序簽核中的應(yīng)用
2021年電子技術(shù)應(yīng)用第11期
孫 恒,,王仁平,,蔡沅坤
福州大學(xué) 物理與信息工程學(xué)院,,福建 福州350000
摘要: 在芯片的設(shè)計過程中,,靜態(tài)時序分析(Static Timing Analysis,,STA)無疑是整個設(shè)計中最重要的一環(huán),。如今納米級工藝下的芯片設(shè)計往往屬于多工藝角多模式(MultiCorner-MultiMode,,MCMM)物理設(shè)計,,工藝角和工作模式的特定組合稱之為場景,,多場景的物理設(shè)計會給芯片帶來更加穩(wěn)定的性能,,但也會使靜態(tài)時序分析變得更為復(fù)雜。介紹了分布式多場景時序分析(Distribute Multi_Scenario Analysis,,DMSA)技術(shù)在多工藝角多模式物理設(shè)計中的應(yīng)用,。經(jīng)過基于Smic 90 nm工藝的多場景數(shù)字芯片Cxdp13設(shè)計實(shí)踐分析表明,在一定硬件條件支撐下,,分布式多場景時序分析技術(shù)在多工藝角多模式的物理設(shè)計中可以達(dá)到快速時序簽核的目的,。
中圖分類號: TN431.2
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.211529
中文引用格式: 孫恒,王仁平,蔡沅坤. DMSA在時序簽核中的應(yīng)用[J].電子技術(shù)應(yīng)用,,2021,,47(11):44-46.
英文引用格式: Sun Heng,Wang Renping,,Cai Yuankun. Application of DMSA in timing sign-off[J]. Application of Electronic Technique,,2021,47(11):44-46.
Application of DMSA in timing sign-off
Sun Heng,,Wang Renping,,Cai Yuankun
Fuzhou University,University of Physics and Information Engineering,,F(xiàn)uzhou 350000,,China
Abstract: In the process of chip design, static timing analysis is undoubtedly the most important part of the entire design, and it is a priority and problem to be solved in chip design. Nowadays, chip design under nano-scale technology often belongs to multicorner-multimode physical design. The specific combination of process angle and working mode is called scenario. Multi-scenario physical design will bring more stable performance to the chip, but it will also make static timing analysis becomes more complicated. This paper introduces the application of distribute multi-scenario analysis technology in multicorner-multimode physical design. The design practice analysis of the multi-scenario digital chip Cxdp13 based on the Smic 90 nm process shows that under certain hardware conditions, the distribute multi_scenario analysis technology can achieve the purpose of rapid timing sign-off in the physical design of multicorner-multimode.
Key words : distribute multi-scenario analysis;static timing analysis,;multicorner-multimode,;timing sign-off;timing engineer change order

0 引言

    隨著集成電路產(chǎn)業(yè)不斷發(fā)展,,芯片制造早已進(jìn)入深亞微米時代,,一直以來,時序簽核一直是檢驗(yàn)芯片設(shè)計是否合格的重要標(biāo)準(zhǔn)之一,,在綜合工具(Design Compiler,,DC)、布局布線工具(Integrated Circuit Compiler,,ICC),、時序分析工具(Prime Time,PT)中都嵌入了不同的時序分析引擎,。當(dāng)工藝節(jié)點(diǎn)達(dá)到90 nm及以下時,,為了使芯片在不同的極端環(huán)境下可以正常工作,就需要采用多工藝角多模式的物理設(shè)計方案來確保芯片在不同環(huán)境下穩(wěn)定工作[1-3],。在對多場景物理設(shè)計進(jìn)行時序分析時,傳統(tǒng)PT需要打開多個窗口反復(fù)切換場景以達(dá)到遍歷每一個場景的目的,,隨后逐個場景進(jìn)行時序分析,,這樣會使設(shè)計過程變得過于繁瑣,而且,,對于同一路徑,,不同場景下的時序違規(guī)可能會重復(fù)出現(xiàn),對時序分析帶來不必要的麻煩[4],,工藝角或模式的合并,,也會帶來各種各樣的問題,DMSA的使用可以很好地解決這些問題。




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作者信息:

孫  恒,,王仁平,蔡沅坤

(福州大學(xué) 物理與信息工程學(xué)院,,福建 福州350000)




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