中圖分類號： TN402 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.229806 中文引用格式： 歐陽可青,，王彬,，魏琦，等. 基于Liberate+Tempus的先進老化時序分析方案[J].電子技術(shù)應(yīng)用,，2022,，48(8)：60-64，69. 英文引用格式： Ouyang Keqing,，Wang Bin,，Wei Qi，et al. Advanced aging-aware STA solution based on Liberate+Tempus[J]. Application of Electronic Technique,，2022,，48(8)：60-64，69.
Advanced aging-aware STA solution based on Liberate+Tempus
1.Department of Back-End Design,，Sanechips Technology Co.，Ltd.,，Shenzhen 518055,，China； 2.State Key Laboratory of Mobile Network and Mobile Multimedia Technology,，Shenzhen 518055,，China； 3.Shanghai Cadence Electronics Technology Co.,，Ltd.,，Shanghai 200000，China
Abstract： At the advanced process nodes(7 nm,，5 nm and belows), circuit aging has become a neck problem that restricts chip performance and reliability. The aging effects may cause increasing cell delay, and thus led to the risk of path timing violation. The IC design engineers need to predict the aging timing in the timing analysis and set some aging margin accordingly to ensure the reliable operation of the chip during the service life-time. In view of this, this paper introduces an advanced aging-aware STA solution based on Liberate+Tempus. Evaluation results show that this solution can release the over-designed time margin while keeping the analysis efficiency, the accuracy, as well as the multi-situation analysis capability, thus providing a powerful basis for achieving advanced chip design with higher reliability and better performance.
Key words : chip aging,；static timing analysis；Tempus,；aging-aware STA
0 引言
在數(shù)字電路物理設(shè)計中,，隨著晶體管特征尺寸不斷減小到7 nm、5 nm及以下,，器件性能對老化的敏感度急劇增加,，電路老化已經(jīng)成為制約芯片性能和可靠性的關(guān)鍵問題。研究表明,，以偏置溫度不穩(wěn)定性(Bias Temperature Instability,，BTI)和熱載流子效應(yīng)(Hot Carrier Injection,，HCI)為主的老化效應(yīng)將導(dǎo)致標準單元(可稱為cell)延時增大，進而產(chǎn)生路徑時序違例的風險[1-3],。對此,，IC設(shè)計工程師需要在芯片物理實現(xiàn)階段即進行考慮老化的時序分析，通過設(shè)置針對性的時序裕量(margin)來覆蓋老化后的惡劣時序場景,，確保芯片在服役期限中可靠運行,。在先進工藝芯片設(shè)計中，精確的老化時序分析并確認合理的margin是一個關(guān)鍵問題,。偏大的margin會導(dǎo)致過設(shè)計,，帶來額外成本并限制芯片性能，而偏小的margin會導(dǎo)致欠設(shè)計,，造成失效泄露的風險,。
本文利用基于Liberate+Tempus 的aging-aware STA 方案進行先進芯片的老化時序分析，評估其效率,、準確性以及針對多樣應(yīng)用場景的老化時序分析能力,。
