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自適應(yīng)定階的快速Burg算法設(shè)計(jì)與FPGA實(shí)現(xiàn)
2021年電子技術(shù)應(yīng)用第11期
郭鳴晗1,,陳立平2,,張 浩2,,趙 坤2,柏 偉1
1.中國科學(xué)院大學(xué),,北京100049;2.中國科學(xué)院微電子研究所,,北京100029
摘要: 針對(duì)信號(hào)頻譜分析的實(shí)時(shí)性要求,,設(shè)計(jì)了一種適用于短序列的自適應(yīng)定階的快速Burg算法硬件加速電路。以FPGA為平臺(tái)進(jìn)行實(shí)驗(yàn),,將快速Burg算法與最終預(yù)測(cè)誤差(Final Prediction Error,,F(xiàn)PE)準(zhǔn)則結(jié)合可做到自回歸(Auto-Regressive,AR)參數(shù)自適應(yīng)定階,。實(shí)現(xiàn)了靈活控制的并行二級(jí)流水線結(jié)構(gòu)和并行化計(jì)算單元,,同時(shí)優(yōu)化了存儲(chǔ)單元,達(dá)到速度與面積的平衡,。實(shí)驗(yàn)結(jié)果表明,,該算法對(duì)短序列也能準(zhǔn)確地估計(jì)信號(hào)頻率,與Burg算法硬件實(shí)現(xiàn)方案的計(jì)算時(shí)間對(duì)比,,該算法將運(yùn)算時(shí)間降低了75%,,確實(shí)起到了加速作用,并且節(jié)省了內(nèi)存空間,,符合設(shè)計(jì)要求,。
中圖分類號(hào): TN911.72;TN4
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.211411
中文引用格式: 郭鳴晗,,陳立平,,張浩,等. 自適應(yīng)定階的快速Burg算法設(shè)計(jì)與FPGA實(shí)現(xiàn)[J].電子技術(shù)應(yīng)用,,2021,,47(11):62-67,72.
英文引用格式: Guo Minghan,,Chen Liping,,Zhang Hao,et al. Design and FPGA implementation of fast Burg algorithm of adaptive order determination[J]. Application of Electronic Technique,,2021,,47(11):62-67,72.
Design and FPGA implementation of fast Burg algorithm of adaptive order determination
Guo Minghan1,,Chen Liping2,,Zhang Hao2,Zhao Kun2,,Bai Wei1
1.University of Chinese Academy of Sciences,,Beijing 100049,China,; 2.Institute of Microelectronics of Chinese Academy of Sciences,,Beijing 100029,,China
Abstract: Aiming to real-time requirement of signal spectrum analysis, an adaptive ordering of fast Burg algorithm hardware acceleration circuit for short sequence based on FPGA is designed. The fast Burg algorithm combined with FPE criterion can be used to determine the order of AR parameters. The parallel two-stage pipeline structure with flexible control is realized, and the parallel computing unit is parallelized. At the same time, the storage unit is optimized to achieve the balance between speed and area. The test show that the algorithm can accurately estimate the signal frequency for short sequences. Compared with the calculation time of Burg algorithm hardware implementation scheme, this algorithm reduces the calculation time by 75%, which does play a role of acceleration, and saves memory space. So, this design meets the design requirements.
Key words : AR parameter model;Burg algorithm,;fast Burg algorithm,;FPGA;hardware acceleration

0 引言

    現(xiàn)代功率譜估計(jì)的AR模型法使用有限長(zhǎng)的數(shù)據(jù)序列來估計(jì)假設(shè)模型的參數(shù),,再將參數(shù)帶入功率譜密度模型中,,可獲得較好的功率譜估計(jì)結(jié)果[1-3]

    Burg算法是一種常見的AR模型求功率譜的方法,,其主導(dǎo)思想是利用前后向預(yù)測(cè)誤差功率之和最小的方法來計(jì)算反射系數(shù)k,,然后帶入Levinson遞推,求解AR模型參數(shù)[4-6],。此方法在處理短數(shù)據(jù)時(shí)具有較高的頻率分辨率[7-8],,但求解反射系數(shù)計(jì)算量較大。為了改進(jìn)這一問題,,Vos提出一種快速Burg算法[9],,通過一系列矩陣變換降低了反射系數(shù)求解時(shí)的計(jì)算量,但是不能確定AR模型的階數(shù),,并且串行算法的執(zhí)行耗時(shí)較長(zhǎng),。針對(duì)上述問題,本文將快速Burg算法與FPE準(zhǔn)則[10]結(jié)合,,對(duì)短序列的功率譜估計(jì)實(shí)現(xiàn)自適應(yīng)定階的功能,,達(dá)到較高頻率分辨率,并使用Verilog硬件描述語言設(shè)計(jì)電路,,達(dá)到硬件加速功能[11],。電路結(jié)構(gòu)在二級(jí)流水線的基礎(chǔ)上[12],結(jié)合自適應(yīng)定階方案,,提出一種新的流水線結(jié)構(gòu),,并設(shè)置狀態(tài)機(jī)靈活控制。本文對(duì)計(jì)算單元進(jìn)行并行化處理加速計(jì)算,??紤]速度與面積的折中,針對(duì)算法特點(diǎn)設(shè)計(jì)內(nèi)存讀寫方案,,減少數(shù)據(jù)存儲(chǔ)長(zhǎng)度,,從而減小了存儲(chǔ)單元的面積。




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作者信息:

郭鳴晗1,,陳立平2,張  浩2,,趙  坤2,,柏  偉1

(1.中國科學(xué)院大學(xué),,北京100049;2.中國科學(xué)院微電子研究所,,北京100029)




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