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高速大容量DDR微系統(tǒng)過孔串?dāng)_研究
2021年電子技術(shù)應(yīng)用第11期
張景輝,,曾燕萍,,王夢(mèng)雅,,周倩蓉,閆傳榮
中國(guó)電子科技集團(tuán)公司第五十八研究所,江蘇 無錫214072
摘要: 隨著高速數(shù)字微系統(tǒng)中DDR總線信號(hào)傳輸速率與系統(tǒng)集成度的不斷提高,,過孔串?dāng)_問題成為影響系統(tǒng)信號(hào)完整性的不可忽視的因素之一,。基于電磁耦合理論,,通過建模仿真方法量化分析了過孔串?dāng)_的主要影響因素以及串?dāng)_噪聲對(duì)信號(hào)質(zhì)量的影響,,在此基礎(chǔ)上提出了過孔設(shè)計(jì)的主要原則以及減小串?dāng)_噪聲的優(yōu)化設(shè)計(jì)方法;介紹了一種正反面腔體結(jié)構(gòu)系統(tǒng)級(jí)封裝的信號(hào)處理微系統(tǒng)基板,,結(jié)合JEDEC標(biāo)準(zhǔn)對(duì)DDR3總線進(jìn)行了仿真分析與評(píng)估,,通過以上方法優(yōu)化過孔串?dāng)_大大改善了DDR總線的信號(hào)完整性,驗(yàn)證了該方法的正確性與有效性,。
中圖分類號(hào): TN405.97
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.211356
中文引用格式: 張景輝,,曾燕萍,王夢(mèng)雅,,等. 高速大容量DDR微系統(tǒng)過孔串?dāng)_研究[J].電子技術(shù)應(yīng)用,,2021,47(11):100-104.
英文引用格式: Zhang Jinghui,,Zeng Yanping,,Wang Mengya,et al. Research on via crosstalk in high speed and large capacity DDR microsystems[J]. Application of Electronic Technique,,2021,,47(11):100-104.
Research on via crosstalk in high speed and large capacity DDR microsystems
Zhang Jinghui,Zeng Yanping,,Wang Mengya,,Zhou Qianrong,Yan Chuanrong
China Electronics Technology Group Corporation No.58 Research Institute,,Wuxi 214072,China
Abstract: With the rapid increase of signal transmission rate and integration in high speed and large capacity digital microsystems, the influence of via crosstalk on signal integrity is becoming more and more prominent. Based on electromagnetic coupling theory, factors on via crosstalk and the influence of crosstalk noise on signal integrity are simulated and analyzed quantitatively by establishing simulation models. And some principles of via design and measures to decrease crosstalk noise are proposed. DDR3 bus in a microsystem in SiP(System in Package) technology, in which DDR units are mounted on both faces, is simulated and analyzed based on JEDEC DDR3 standard. Signal integrity of DDR bus is improved distinctly by reducing via crosstalk in a proper and effective measure proposed in this paper.
Key words : via crosstalk,;microsystem,;DDR;signal integrity

0 引言

    采用并行傳輸技術(shù)的雙倍速率同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器(Double Data Rate Synchronous Dynamic Random Access Memory,,DDR SDRAM)是現(xiàn)代高速數(shù)字系統(tǒng)的主流應(yīng)用,,主控芯片與DDR存儲(chǔ)器之間互聯(lián)結(jié)構(gòu)的信號(hào)完整性是保證整個(gè)系統(tǒng)運(yùn)行的關(guān)鍵。DDR拓?fù)涞淖呔€方式,、阻抗匹配,、端接方式、傳輸線的反射與串?dāng)_等問題是決定DDRx并行總線信號(hào)完整性的關(guān)鍵因素,,也是系統(tǒng)設(shè)計(jì)研究的重點(diǎn)[1-3],。

    隨著現(xiàn)代數(shù)字系統(tǒng)數(shù)據(jù)傳輸速率越來越高,系統(tǒng)布線越來越密集,,信號(hào)之間的串?dāng)_問題越來越突出[1],。對(duì)于信號(hào)串?dāng)_的研究主要集中在連接器,、芯片封裝與近間距的平行走線之間,過孔間的串?dāng)_問題是容易被忽略的因素,。然而,,對(duì)于采用系統(tǒng)級(jí)封裝(System in Package,SiP)[4-5]的高速大容量DDR微系統(tǒng)來說,,系統(tǒng)集成度進(jìn)一步提高,,高速多層過孔普遍存在,造成過孔Z方向長(zhǎng)度遠(yuǎn)大于水平方向的間距,,過孔串?dāng)_成為不可忽視的問題,。




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作者信息:

張景輝,,曾燕萍,,王夢(mèng)雅,周倩蓉,,閆傳榮

(中國(guó)電子科技集團(tuán)公司第五十八研究所,,江蘇 無錫214072)





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