基于Cadence Integrity 3D-IC的異構(gòu)集成封裝系統(tǒng)級LVS檢查
2023年電子技術(shù)應(yīng)用第8期
張成,,趙佳,,李晴
(格芯半導(dǎo)體(上海)有限公司 中國研發(fā)中心(上海),上海 201204)
摘要: 隨著硅工藝尺寸發(fā)展到單納米水平,,摩爾定律的延續(xù)越來越困難,。2D Flip-Chip,、2.5D、3D等異構(gòu)集成的先進封裝解決方案將繼續(xù)滿足小型化,、高性能,、低成本的市場需求,成為延續(xù)摩爾定律的主要方向,。但它也提出了新的挑戰(zhàn),,特別是對于系統(tǒng)級的LVS檢查。采用Cadence Integrity 3D-IC平臺工具,,針對不同類型的先進封裝,,進行了系統(tǒng)級LVS檢查驗證,充分驗證了該工具的有效性和實用性,保證了異構(gòu)集成封裝系統(tǒng)解決方案的可靠性,。
中圖分類號:TN402 文獻標(biāo)志碼:A DOI: 10.16157/j.issn.0258-7998.239802
中文引用格式: 張成,,趙佳,李晴. 基于Cadence Integrity 3D-IC的異構(gòu)集成封裝系統(tǒng)級LVS檢查[J]. 電子技術(shù)應(yīng)用,,2023,,49(8):47-52.
英文引用格式: Zhang Cheng,Zhao Jia,,Li Qing. System-level LVS checking of heterogeneous integration packaging based on Cadence Integrity 3D-IC[J]. Application of Electronic Technique,,2023,49(8):47-52.
中文引用格式: 張成,,趙佳,李晴. 基于Cadence Integrity 3D-IC的異構(gòu)集成封裝系統(tǒng)級LVS檢查[J]. 電子技術(shù)應(yīng)用,,2023,,49(8):47-52.
英文引用格式: Zhang Cheng,Zhao Jia,,Li Qing. System-level LVS checking of heterogeneous integration packaging based on Cadence Integrity 3D-IC[J]. Application of Electronic Technique,,2023,49(8):47-52.
System-level LVS checking of heterogeneous integration packaging based on Cadence Integrity 3D-IC
Zhang Cheng,,Zhao Jia,,Li Qing
(Globalfoundries China (Shanghai) Co., Limited,, Shanghai 201204,, China)
Abstract: With the development of silicon process size to the level of single nano, it has been more and more difficult to continue Moore's law. Advanced packaging solutions with heterogeneous integration, such as 2D Flip-Chip, 2.5D and 3D, will continue to meet market requirements for miniaturization, high performance and low cost, thus become the main direction of continuing Moore's Law. But it also presents new challenges, especially for system-level LVS checking. In this paper, Cadence Integrity 3D-IC tool was used to perform system-level LVS checking for different types of advanced packaging, which fully verified the effectiveness and practicability of the tool and ensured the reliability of heterogeneous integration packaging system solutions.
Key words : heterogeneous integration;advanced packaging,;system-level LVS,;integrity 3D-IC
0 引言
電子產(chǎn)品一直以來追求的尺寸更小,成本和功耗更低的趨勢,,在過去受益于硅工藝的快速升級更新,,得到了持續(xù)的發(fā)展。但近年來,,隨著硅工藝尺寸發(fā)展到單納米水平,,摩爾定律的延續(xù)越來越困難。單一的納米工藝在綜合考慮成本,、良率,、功耗等因素后,將不再具有競爭優(yōu)勢,。2D Flip-Chip,、2.5D、3D等具有異構(gòu)集成的先進封裝解決方案將繼續(xù)滿足小型化,、高性能,、低成本的市場需求,成為延續(xù)摩爾定律的主要方向,。但它也提出了新的挑戰(zhàn),,特別是對于系統(tǒng)級的LVS(Layout Versus Schematics)檢查。由于異構(gòu)集成封裝結(jié)構(gòu)復(fù)雜,、規(guī)模龐大,任何一個環(huán)節(jié)的失誤都會產(chǎn)生巨大的影響,因此急需一個完整的解決方案,,可以對各類異構(gòu)集成封裝進行有效的系統(tǒng)級檢查,。本文嘗試采用Cadence公司的Integrity 3D-IC平臺,針對主流的異構(gòu)集成封裝進行LVS檢查驗證,。
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作者信息:
張成,,趙佳,李晴
(格芯半導(dǎo)體(上海)有限公司 中國研發(fā)中心(上海),,上海 201204)
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