中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.240802 中文引用格式： 汪鋒剛,，晉亞緊,，周國華,，等. 基于Cerebrus的Genus+Innovus流程的功耗面積優(yōu)化[J]. 電子技術(shù)應(yīng)用，2024,，50(8)：21-25. 英文引用格式： Wang Fenggang,，Jin Yajin，Zhou Guohua,et al. Power consumption area optimization for the Cerebrus-based Genus+Innovus procedure[J]. Application of Electronic Technique,，2024,，50(8)：21-25.
Power consumption area optimization for the Cerebrus-based Genus+Innovus procedure
Wang Fenggang1，Jin Yajin1,，Zhou Guohua1,，2，Liu Yuzheng3
1.Department of Back-End Design,， Sanechips Technology Co.,， Ltd.,； 2.State Key Laboratory of Mobile Network and Mobile Multimedia Technology； 3.Cadence Design Systems,， Inc.
Abstract： The pursuit of performance,，power and area (PPA) has become the consensus of IC chip design, especially the development to advanced process nodes. PPA has become a crucial metric of overall performance of IC design. Especially for the modules cloned numerous times in large-scale SoC chips, the pursuit of PPA becomes more extreme. This document describes how to improve the PPA optimization solution based on the Genus and Cerebrus tools of Cadence and the optimization of the Synthesis and the Back-End PR stage. The final result shows that, under the convergence of timing and DRC, employing the Cerebrus tool compared to Innovus can reduce power by 3.5% and area by 3.1%. Furthermore, utilizing the Genus+Innovus flow can reduce power by 6.4% and area by 8.5%, significantly decreasing chip area and power.
Key words : chip design；Genus tool,；Cerebrus tool,；PPA optimization
