采購員謹防：輸出擺幅達到最大值之前，線性就已經(jīng)開始下降,。
單電源運算放大器不能真正實現(xiàn)輸出的軌對軌擺動,。接近軌時，放大器呈現(xiàn)出非線性,。對線性工作,，單電源放大器的輸出每軌都能達到50到300mV（圖1）。
單電源放大器,，軌對軌輸出的廣告造成安全的錯覺,。圖1顯示了驅(qū)動軌輸出時，典型單電源放大器的輸出擺幅,。
在輸出擺幅達到最大值之前,，放大器的線性就已經(jīng)開始大幅下降，放大器輸出不能達到任何電源電壓,。
為使直流開環(huán)增益指標達到要求,，只有假設放大器處于線性工作輸出范圍。直流開環(huán)增益用分貝表示為20 log(ΔVOUT/ΔVOS),，其中VOUT為電壓輸出,，VOS為輸入偏置電壓,。驅(qū)動輸出為高時,，VH為輸出直流開環(huán)增益測量的最大電壓。VOH為相對于輸出所能達到VDD的絕對電壓最大值,。VL為輸出直流開環(huán)增益測量的最小電壓,，VOL為輸出所能達到的絕對電壓最小值。VH小于VOH,，而VL大于VOL,。
從信號流的觀點看，運算放大器驅(qū)動ADC時,，輸出限制軌對軌擺幅,。圖2a中FFT圖顯示了5V系統(tǒng)中,，放大器結合ADC對1KHz信號的響應。放大器典型的閉環(huán)帶寬約為3MHz,，上升速率為2.3V/µsec,。放大器輸出電壓在140 mV到4.66V擺動。在5V供電系統(tǒng)中,，信號到電源的差距為140 mV,。對這個放大器，VOL最小為比地電壓高15 mV,，而VOH最大為VDD–20 mV,。
圖2a通過顯示2、3,、4kHz等頻率下的失真,，說明了單電源供電的CMOS放大器輸出范圍的非線性。通過減少每個軌的放大器輸出信號到272 mV,，在僅有ADC失真時數(shù)據(jù)理想,。(圖2b)
使用單電源運放,，要仔細閱讀手冊。一些單電源運放有輸出域電荷泵,，允許放大器輸出擺動達到和超出供電電源軌,。在任何情況下，務必要讀數(shù)據(jù)手冊和參考開環(huán)增益測試條件,。
英文原文：
Single-supply amplifier outputs don't swing rail to rail
Buyer beware: Linearity starts to degrade long before reaching the output-swing maximums.
By Bonnie Baker -- EDN, 9/3/2007
Single-supply amplifiers do not truly swing rail to rail at the output. Near the rail, the amplifier is nonlinear. For linear operation, the output of single-supply amplifiers can come within only 50 to 300 mV of each rail (Figure 1).
Single-supply-amplifier, rail-to-rail-output ads can give a false sense of security. Figure 1 shows a typical single-supply amplifier’s output swing as you drive the output to the rails.
The amplifier’s linearity starts to degrade long before reaching the output-swing maximums, and the amplifier output never reaches either rail.
The conditions of the dc-open-loop-gain specification define the amplifier’s linear operating output range. The dc open loop gain in decibels is 20 log(ΔVOUT/ΔVOS), where VOUT is the output voltage and VOS is the input offset voltage. When you drive the output high, VH is the maximum voltage level at the output in the dc-open-loop-gain measurement. VOH is the absolute maximum voltage level with respect to VDD (drain-to-drain voltage) that the output can reach. VL is the minimum voltage level at the output in the dc-open-loop-gain measurement, and VOL is the absolute minimum voltage level that the output can reach. VH is less than VOH, and VL is greater than VOL.
From a signal-chain perspective, you can see an op amp’s output limitations to swinging rail to rail when the op amp is driving an ADC. The FFT plot in Figure 2a shows the amplifier/ADC-combination response to a 1-kHz signal in a 5V system. The amplifier’s ty
pical closed-loop bandwidth is about 3 MHz with a typical slew rate of 2.3V/µsec. The amplifier output voltage swings from 140 mV to 4.66V. In this 5V-supply system, the headroom between the signal and rails is 140 mV. For this amplifier, the VOL minimum specification is 15 mV above ground. The VOH maximum specification is VDD–20 mV.
Figure 2a illustrates the nonlinearity-output-stage effects with a single-supply CMOS amplifier by showing distortion at 2, 3, and 4 kHz and so on. By reducing the amplifier’s output signal to 272 mV from each rail, the data looks perfect with only the ADC distortion (Figure 2b).
When using a single-supply amplifier, read the fine print! Some single-supply amps have output-stage charge pumps, allowing the amplifier’s output swing to go to and well beyond the power-supply rails. In every case, read your data sheet and refer to the conditions on the open-loop-gain test.