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一種基于Ring-VCO結(jié)構(gòu)的寬頻帶低抖動(dòng)鎖相環(huán)的設(shè)計(jì)與實(shí)現(xiàn)
2020年電子技術(shù)應(yīng)用第5期
劉 穎1,,田 澤1,2,,呂俊盛1,,2,,邵 剛1,2,,胡曙凡1,,李 嘉1
1.航空工業(yè)西安航空計(jì)算技術(shù)研究所,陜西 西安710068,; 2.集成電路與微系統(tǒng)設(shè)計(jì)航空科技重點(diǎn)實(shí)驗(yàn)室,,陜西 西安710068
摘要: 為了在高速傳輸系統(tǒng)中實(shí)現(xiàn)寬頻帶和低抖動(dòng)時(shí)鐘輸出的要求,設(shè)計(jì)了一種基于Ring-VCO結(jié)構(gòu)的低抖動(dòng)鎖相環(huán),,采用與鎖相環(huán)鎖定頻率強(qiáng)相關(guān)的環(huán)路帶寬調(diào)整方法來(lái)降低環(huán)路噪聲,,加速環(huán)路鎖定,即利用全局參考調(diào)節(jié)電路中比較器模塊將鎖定控制電壓與參考電壓比較來(lái)改變各模塊電流,,根據(jù)不同鎖定頻率調(diào)整環(huán)路參數(shù),,大大縮短了鎖定時(shí)間,,同時(shí)利用四級(jí)差分環(huán)形振蕩器和占空比調(diào)整電路的差分對(duì)稱結(jié)構(gòu),,降低了電路噪聲。電路采用40 nm CMOS工藝實(shí)現(xiàn),,測(cè)試結(jié)果表明輸出頻率為1.062 5 GHz~5 GHz,,在最高時(shí)鐘頻率5 GHz下眼圖質(zhì)量良好,時(shí)鐘抖動(dòng)39.6 ps,。
中圖分類號(hào): TN432
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.191337
中文引用格式: 劉穎,,田澤,呂俊盛,,等. 一種基于Ring-VCO結(jié)構(gòu)的寬頻帶低抖動(dòng)鎖相環(huán)的設(shè)計(jì)與實(shí)現(xiàn)[J].電子技術(shù)應(yīng)用,,2020,46(5):35-39.
英文引用格式: Liu Ying,,Tian Ze,,Lv Junsheng,et al. Design and implement of a ring-VCO based PLL with wide frequency range and low jitter[J]. Application of Electronic Technique,,2020,,46(5):35-39.
Design and implement of a ring-VCO based PLL with wide frequency range and low jitter
Liu Ying1,,Tian Ze1,2,,Lv Junsheng1,,2,Shao Gang1,,2,,Hu Shufan1,Li Jia1
1.AVIC Computing Technique Research Institute,,Xi′an 710068,,China; 2.Aviation Key Laboratory of Science and Technology on Integrated Circuit and Micro-System Design,,Xi′an 710068,,China
Abstract: A ring-VCO based phase lock loop(PLL) is designed for achieving the wide frequency range and low jitter requirements of high speed communication system. By adjusting the loop bandwidth which is closely related to the lock-in frequency it reduces the loop noise and accelerates loop locking. Adopting the comparator in reference circuit to compare the locking control voltage with the reference voltage to flexibly change the current in other module, and adjusting the loop parameters according to different lock-in frequencies, the lock-in time is greatly reduced. At the same time, the differential symmetrical structure of the four-stage differential ring oscillator and duty cycle adjusting circuit is used to reduce the circuit noise. This chip is fabricated in 40 nm CMOS process, the measured results show that the output frequency is from 1.062 5 GHz to 5 GHz, the performance of the signal at 5 GHz is good and jitter is 39.6 ps.
Key words : phase lock loop;ring oscillator,;wide frequency range,;low jitter

0 引言

    鎖相環(huán)作為時(shí)鐘產(chǎn)生的核心電路,以其寬頻帶,、低抖動(dòng),、鎖定速度快等特點(diǎn),被廣泛應(yīng)用在高速通信和電子傳輸系統(tǒng)中,。最早的電荷泵鎖相環(huán)電路固定環(huán)路帶寬實(shí)現(xiàn),,輸出時(shí)鐘頻帶較窄,鎖定時(shí)間較長(zhǎng),。隨著高速,、多協(xié)議的通信系統(tǒng)的快速發(fā)展,要求鎖相環(huán)電路輸出頻率范圍廣及時(shí)鐘抖動(dòng)低,,而固定環(huán)路帶寬的鎖相環(huán)電路結(jié)構(gòu)無(wú)法同時(shí)滿足輸出頻率范圍,、各頻點(diǎn)鎖定時(shí)間及噪聲的要求[1-2],因此,,鎖相環(huán)電路環(huán)路參數(shù)可調(diào)已成為主流電路結(jié)構(gòu)[3-5],。常見(jiàn)的環(huán)路帶寬可調(diào)通過(guò)寄存器配置電荷泵、環(huán)路濾波器參數(shù)等方式實(shí)現(xiàn),,此類方法易實(shí)現(xiàn),,但操作較為機(jī)械,且與鎖定頻率非強(qiáng)相關(guān),,性能無(wú)法達(dá)到最優(yōu),。

    因此,為了能夠拓寬鎖相環(huán)輸出頻帶,同時(shí)滿足輸出低抖動(dòng)時(shí)鐘的要求,,本文提出了一種與鎖相環(huán)鎖定頻率強(qiáng)相關(guān)的環(huán)路帶寬調(diào)整方法,,利用全局參考調(diào)節(jié)電路中比較器模塊將鎖定控制電壓Vctrl與參考電壓Vref電壓比較來(lái)改變各模塊電流,實(shí)現(xiàn)不同頻率下環(huán)路帶寬的調(diào)整,,加速環(huán)路鎖定,,降低鎖相環(huán)噪聲。另一方面,,采用四級(jí)差分環(huán)形振蕩器結(jié)構(gòu)和占空比調(diào)整電路,,以其差分對(duì)稱結(jié)構(gòu)降低電路噪聲,并在電路中引入LDO等方式進(jìn)行抖動(dòng)優(yōu)化[6-9],。




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作者信息:

劉  穎1,,田  澤1,2,,呂俊盛1,,2,邵  剛1,,2,,胡曙凡1,李  嘉1

(1.航空工業(yè)西安航空計(jì)算技術(shù)研究所,,陜西 西安710068,;

2.集成電路與微系統(tǒng)設(shè)計(jì)航空科技重點(diǎn)實(shí)驗(yàn)室,陜西 西安710068)

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