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一種基于國產(chǎn)嵌入式CPU核的BP神經(jīng)網(wǎng)絡(luò)SoC設(shè)計(jì)
2021年電子技術(shù)應(yīng)用第4期
徐文亮
杭州電子科技大學(xué) 電子信息學(xué)院,浙江 杭州310018
摘要: 基于國產(chǎn)嵌入式CPU核CK803S及其SoC設(shè)計(jì)平臺(tái),,設(shè)計(jì)一款BP神經(jīng)網(wǎng)絡(luò)SoC,。給出了SoC的設(shè)計(jì)結(jié)構(gòu)及BP神經(jīng)網(wǎng)絡(luò)硬件加速器的設(shè)計(jì)方案,,針對(duì)BP神經(jīng)網(wǎng)絡(luò)硬件加速器中非線性的Sigmod和Guass激活函數(shù),選擇了一種既不影響速度又節(jié)約資源的方法來實(shí)現(xiàn),,并對(duì)其性能,、功耗進(jìn)行優(yōu)化。驗(yàn)證結(jié)果表明,,設(shè)計(jì)滿足要求,。
中圖分類號(hào): TN47;TN492
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.200949
中文引用格式: 徐文亮. 一種基于國產(chǎn)嵌入式CPU核的BP神經(jīng)網(wǎng)絡(luò)SoC設(shè)計(jì)[J].電子技術(shù)應(yīng)用,,2021,,47(4):63-66.
英文引用格式: Xu Wenliang. Design of a BP neural network SoC based on domestic embedded CPU[J]. Application of Electronic Technique,2021,,47(4):63-66.
Design of a BP neural network SoC based on domestic embedded CPU
Xu Wenliang
School of Electronic Information,,Hangzhou Dianzi University,Hangzhou 310018,,China
Abstract: The paper designs a Back Propagation(BP)neural network system on chip(SoC) based on the domestic embedded Central Processing Unit(CPU) CK803S and its SoC design platform. The design structure of SoC and the design scheme of BP neural network hardware accelerator are given, and for the non-linear BP activation functions Sigmod and Guass, a method that can save hardware resources while not affect the speed is selected to implement them,and optimize accelerator′s performance and power consumption.The verification results show that the design can meet the requirements.
Key words : BP neural network,;domestic embedded processor CK803S;SoC design platform,;FPGA implement

0 引言

    人工神經(jīng)網(wǎng)絡(luò)的實(shí)現(xiàn)方法主要分為硬件實(shí)現(xiàn)[1]和軟件實(shí)現(xiàn)[2]兩種,。神經(jīng)網(wǎng)絡(luò)軟件實(shí)現(xiàn)的方法具有并行度低和實(shí)現(xiàn)速度慢的特點(diǎn),并且不能滿足神經(jīng)網(wǎng)絡(luò)對(duì)實(shí)時(shí)運(yùn)算的要求,。除此之外,,最大的缺點(diǎn)是用軟件模擬實(shí)現(xiàn)的方法需要龐大體積的計(jì)算機(jī)作支持,這樣就很不適合應(yīng)用于嵌入式場(chǎng)景,?;谟布?shí)現(xiàn)的神經(jīng)網(wǎng)絡(luò)具有運(yùn)算速度快、并行性高等優(yōu)點(diǎn)[3],,并且在實(shí)時(shí)運(yùn)算方面也能滿足要求,。綜合考慮,本文采用硬件實(shí)現(xiàn)的方法來設(shè)計(jì)人工神經(jīng)網(wǎng)絡(luò),。

    本文設(shè)計(jì)的目的是找到一種方法——硬件實(shí)現(xiàn)的神經(jīng)網(wǎng)絡(luò)能夠進(jìn)行動(dòng)態(tài)調(diào)節(jié),既可以實(shí)現(xiàn)神經(jīng)網(wǎng)拓?fù)浣Y(jié)構(gòu)的動(dòng)態(tài)調(diào)節(jié),,即每層網(wǎng)絡(luò)和每層神經(jīng)元的個(gè)數(shù)動(dòng)態(tài)可調(diào),,也可以實(shí)現(xiàn)輸入權(quán)值和閾值的自動(dòng)更新。本文以BP神經(jīng)網(wǎng)絡(luò)為例,,使用國產(chǎn)嵌入式CPU CK803S及其SoC設(shè)計(jì)平臺(tái)SmartL-Prime,,實(shí)現(xiàn)一款BP神經(jīng)網(wǎng)絡(luò)SoC的設(shè)計(jì)。




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作者信息:

徐文亮

(杭州電子科技大學(xué) 電子信息學(xué)院,,浙江 杭州310018)

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