中圖分類號： TN47,；TN492 文獻標(biāo)識碼： A DOI：10.16157/j.issn.0258-7998.200949 中文引用格式： 徐文亮. 一種基于國產(chǎn)嵌入式CPU核的BP神經(jīng)網(wǎng)絡(luò)SoC設(shè)計[J].電子技術(shù)應(yīng)用,，2021，47(4)：63-66. 英文引用格式： Xu Wenliang. Design of a BP neural network SoC based on domestic embedded CPU[J]. Application of Electronic Technique,，2021,，47(4)：63-66.
Design of a BP neural network SoC based on domestic embedded CPU
Xu Wenliang
School of Electronic Information，Hangzhou Dianzi University,，Hangzhou 310018,，China
Abstract： The paper designs a Back Propagation(BP)neural network system on chip(SoC) based on the domestic embedded Central Processing Unit(CPU) CK803S and its SoC design platform. The design structure of SoC and the design scheme of BP neural network hardware accelerator are given, and for the non-linear BP activation functions Sigmod and Guass, a method that can save hardware resources while not affect the speed is selected to implement them,and optimize accelerator′s performance and power consumption.The verification results show that the design can meet the requirements.
Key words : BP neural network；domestic embedded processor CK803S,；SoC design platform,；FPGA implement
