中圖分類號： TN492 文獻(xiàn)標(biāo)識碼： A DOI：10.16157/j.issn.0258-7998.201078 中文引用格式： 李芳,，焦繼業(yè)，馬彩彩. 基于 HVCMOS工藝的H橋驅(qū)動電路版圖設(shè)計[J].電子技術(shù)應(yīng)用,，2021,，47(6)：35-39. 英文引用格式： Li Fang，Jiao Jiye,，Ma Caicai. H-bridge driver circuit layout design based on HVCMOS technology[J]. Application of Electronic Technique,，2021，47(6)：35-39.
H-bridge driver circuit layout design based on HVCMOS technology
Li Fang,，Jiao Jiye,，Ma Caicai
College of Electronic Engineer，Xi′an University of Posts and Telecommunications,，Xi′an 710000,，China
Abstract： The design and realization of a H-bridge which is power integrated circuit(Power IC, PIC) and based on the HVCMOS process with low cost, high integration and strong driving performance is introduced. The established metal interconnection evaluation model can judge the H-bridge physical layout in the early stage of the design and does not rely on post-design simulation, thereby improving design efficiency.The comparison result of different interconnection design of H-bridge shows that the interconnection of multi-finger array device(M2 layer and above metal) is perpendicular to the metal layer M1 of the device and ladder-shaped structure can improve the effective aspect ratio of the interconnection along the current flow direction, thus reduce parasitic resistance.
Key words : HVCMOS,；H-bridge；high integration,；low on-resistance
