中圖分類號(hào)： TN401 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.211700 中文引用格式： 楊楚瑋，張梅娟,，侯慶慶. 基于FPGA的SiP原型驗(yàn)證平臺(tái)設(shè)計(jì)[J].電子技術(shù)應(yīng)用,，2022，48(1)：84-88,，93. 英文引用格式： Yang Chuwei,，Zhang Meijuan，Hou Qingqing. The designation of SiP prototype verification platform based on FPGA[J]. Application of Electronic Technique,，2022,，48(1)：84-88，93.
The designation of SiP prototype verification platform based on FPGA
Yang Chuwei,，Zhang Meijuan,，Hou Qingqing
The 58th Research Institute，CETC,，Wuxi 214035,，China
Abstract： With the growing demand of embedded system miniaturization and the performance of analog-to-digital/digital-to-analog converter(ADC/DAC), it is a big problem how to improve the reliability of ADC/DAC signal transmission, increase the function configurability and signal processing reconfigurability on the premise of reducing system volume and power consumption. Thus, this paper designs a system in package(SiP) prototype verification platform based on FPGA, used to verify the feasibility and reliability of this SiP architecture.
Key words : prototype verification；reconfigurable algorithm,；bare machines IP,；FPGA
