《電子技術(shù)應(yīng)用》
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一種新型自毀芯片監(jiān)測(cè)和執(zhí)行電路的設(shè)計(jì)
2022年電子技術(shù)應(yīng)用第2期
胡長(zhǎng)征,,馬 偉,,高清運(yùn),,胡偉波
南開大學(xué) 電子信息與光學(xué)工程學(xué)院,,天津300350
摘要: 針對(duì)當(dāng)前自毀技術(shù)中,自毀監(jiān)測(cè)方式單一且自毀執(zhí)行較長(zhǎng)和自毀不徹底,、不穩(wěn)定導(dǎo)致自毀成功率較低的問題,,設(shè)計(jì)了一種同時(shí)具備自毀實(shí)時(shí)監(jiān)測(cè)和執(zhí)行的電路系統(tǒng)。該電路系統(tǒng)設(shè)計(jì)了封裝拆卸和上電時(shí)序兩種自毀監(jiān)測(cè)方式,,使自毀監(jiān)測(cè)的方式更加多樣,,提高結(jié)果的準(zhǔn)確性。同時(shí)利用MOS管作為開關(guān)特性,,來減少自毀執(zhí)行的時(shí)間,。實(shí)驗(yàn)結(jié)果表明,該電路系統(tǒng)在3.3 V的供電電壓且鉭電容存儲(chǔ)電壓為20 V時(shí),,可以通過自毀監(jiān)測(cè)電路對(duì)工作芯片進(jìn)行實(shí)時(shí)的監(jiān)測(cè),,同時(shí)經(jīng)過測(cè)試表明,,從監(jiān)測(cè)到自毀信號(hào)到自毀執(zhí)行開始,,需要時(shí)間為0.28 ms。
中圖分類號(hào): TN409
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.211819
中文引用格式: 胡長(zhǎng)征,,馬偉,,高清運(yùn),等. 一種新型自毀芯片監(jiān)測(cè)和執(zhí)行電路的設(shè)計(jì)[J].電子技術(shù)應(yīng)用,2022,,48(2):23-27.
英文引用格式: Hu Changzheng,,Ma Wei,Gao Qingyun,,et al. Design of a new type of self-destruct chip monitoring and execution circuit[J]. Application of Electronic Technique,,2022,48(2):23-27.
Design of a new type of self-destruct chip monitoring and execution circuit
Hu Changzheng,,Ma Wei,,Gao Qingyun,Hu Weibo
College of Electronic Information and Optical Engineering,,Nankai University,,Tianjin 300350,China
Abstract: In the current self-destruction technology, the self-destruction monitoring method is single, the self-destruction execution is long, and the self-destruction is incomplete and unstable, which leads to the low success rate of self-destruction. A real-time monitoring and execution circuit system with both self-destruction monitoring and execution is designed. The circuit system designed two self-destruct monitoring methods, packaging and disassembly and power-on timing, which made the self-destruct monitoring methods more diverse and the results more accurate. At the same time, MOS tube was used as the switching characteristic to reduce the time of self-destruct execution. The experimental results show that the circuit system can carry out real-time monitoring of the working chip through the self-destruct monitoring circuit when the supply voltage is 3.3 V and the storage voltage of tantalum capacitor is 20 V. Meanwhile, the test results show that the time from the monitoring to the self-destruct signal to the start of the self-destruct execution is 0.28 ms.
Key words : self-destruction chip,;real-time self-destruction monitoring,;self-destruction execution

0 引言

    當(dāng)前自毀技術(shù)應(yīng)用廣泛,在無人機(jī)的偵察系統(tǒng),、機(jī)密數(shù)據(jù)的存儲(chǔ)設(shè)備[1]以及關(guān)鍵芯片,、電子政務(wù)和金融等領(lǐng)域都有很好的應(yīng)用[2]。2016年,,Jin-Woo Han等人提出了一種自毀式鰭片觸發(fā)器驅(qū)動(dòng)的晶體管,,在需要芯片自毀時(shí),向觸發(fā)柵極施加觸發(fā)電壓,,產(chǎn)生的靜電彎曲應(yīng)力將破壞鰭片的源-漏延伸區(qū)域,,使晶體管斷開,電路失去原本功能,。2017年,,解放軍海軍醫(yī)學(xué)研究所提出一種新的自觸發(fā)方法,這種方法是在監(jiān)測(cè)電路感知到設(shè)備外殼上的螺絲被擰下時(shí)[3],,產(chǎn)生高電流信號(hào)使芯片燒毀,。2018年長(zhǎng)春聞鼓通信公司通過控制端發(fā)出自毀命令[4]時(shí),芯片保護(hù)電路內(nèi)部產(chǎn)生高壓擊毀芯片,,以此達(dá)到防止信息泄露的目的,。

    在大多數(shù)自毀設(shè)計(jì)和應(yīng)用中,自毀監(jiān)測(cè)的方式一直被忽視,,導(dǎo)致自毀監(jiān)測(cè)方式單一,,準(zhǔn)確靈敏性較低。同時(shí)在監(jiān)測(cè)到自毀狀態(tài)到產(chǎn)生自毀信號(hào),,開始執(zhí)行自毀的整個(gè)過程時(shí)間較長(zhǎng),,且其自毀程度不夠徹底,,有時(shí)只能停止電路的正常工作,不能真正地破壞芯片數(shù)據(jù)的存儲(chǔ)模塊,。

    本設(shè)計(jì)針對(duì)自毀監(jiān)測(cè)方式和自毀信號(hào)產(chǎn)生速度的問題,,基于閾值判斷等算法[5],提出了一種新型自毀芯片監(jiān)測(cè)和執(zhí)行電路系統(tǒng),,可以通過封裝拆卸和上電時(shí)序[6],,對(duì)芯片工作環(huán)境進(jìn)行監(jiān)測(cè),同時(shí)利用閾值判斷等算法對(duì)監(jiān)測(cè)數(shù)據(jù)進(jìn)行分析和處理,,產(chǎn)生自毀執(zhí)行信號(hào),,在較短的時(shí)間內(nèi)執(zhí)行自毀。




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作者信息:

胡長(zhǎng)征,,馬  偉,高清運(yùn),,胡偉波

(南開大學(xué) 電子信息與光學(xué)工程學(xué)院,,天津300350)




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