中國分類號： TN6 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.212068 中文引用格式： 趙前,，羅通頂，陳彥麗,，等. 高性能數(shù)據(jù)采集系統(tǒng)核心器件國產(chǎn)化水平研究[J].電子技術應用,，2022，48(5)：7-11,，20. 英文引用格式： Zhao Qian,，Luo Tongding，Chen Yanli，et al. Research of data acquisition instrument based on domestic key chip[J]. Application of Electronic Technique,，2022,，48(5)：7-11，20.
Research of data acquisition instrument based on domestic key chip
State Key Lab of Intense Pulsed Radiation Simulation and Effect，Northwest Institute of Nuclear Technology,，Xi′an 710024,，China
Abstract： The high performance data acquisition system is widely used in scientific research such as high energy physics, particle physics experiment and radiation detection, which is the key equipment of many large scientific experiment. The core devices of data acquisition instrument mainly include ADC and FPGA which are monopolized by developed countries for a long time. Especially high-performance ADC and FPGA, which are strictly relevant to China′s technology contractions, so it’s important to research the high performance data acquisition system based on the core devices of the domestic. The paper sketches the embargo on the equipment of core electronic components and key instruments based on the " Wassenaar Arrangement " and the theory of high performance data acquisition system. This paper researches the production status of the domestic high-performance ADC and FPGA, and makes the performance comparison. After that, the present situation of the oscilloscope and the data acquisition instrument are compared. Finally, the paper discusses the substitution of core electronic components.
Key words : Wassenaar arrangement；data acquisition system,；ADC,；FPGA
數(shù)據(jù)采集系統(tǒng)結構如圖1所示,，首先模擬信號經(jīng)過前置模擬電路進行預處理,，如單端輸入轉差分電路等，經(jīng)調(diào)理過的模擬信號進入模數(shù)轉換器(Analog to Digital Converter,，ADC)芯片進行模數(shù)轉換,，ADC輸出量化編碼至現(xiàn)場可編程邏輯門陣列(Field Programmable Gate Array,，FPGA)芯片，當ADC輸出的采樣數(shù)據(jù)率高于FPGA內(nèi)部邏輯資源的處理速率時,，F(xiàn)PGA不能直接接收數(shù)據(jù)進入其內(nèi)部邏輯資源,，這時需要對ADC的輸出數(shù)據(jù)進行接收轉換、延時調(diào)整和降速處理等操作,，才能進入FPGA內(nèi)部處理,，再通過外部總線協(xié)議讀取DDR或FPGA內(nèi)部的緩存數(shù)據(jù)做在線數(shù)據(jù)分析或離線數(shù)據(jù)分析，數(shù)據(jù)采集系統(tǒng)還包括一些外圍電路,，比如前端模擬電路,、時鐘電路、外觸發(fā)模塊及電源模塊等[1-4],。
