中圖分類號(hào)： TN402 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.222775 中文引用格式： 王可揚(yáng),，吉兵,，屈凌翔. 一種用于PCIe多通道的De-skew電路設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2022,，48(11)：63-66,，73. 英文引用格式： Wang Keyang,，Ji Bing,，Qu Lingxiang. De-skew circuit design for PCIe multi-lane[J]. Application of Electronic Technique，2022,，48(11)：63-66,，73.
De-skew circuit design for PCIe multi-lane
Wang Keyang，Ji Bing,，Qu Lingxiang
China Electronics Technology Group Corporation No.58 Research Institute,，Wuxi 214072，China
Abstract： In the process of multi-lane data transmission in PCIe, when the arrival time of data in each lane is inconsistent, the issue of skew will be introduced. In order to ensure that the receiver of each lane can process the received data simultaneously and correctly, it is necessary to preprocess the transmitted data. This paper presents a De-skew logic circuit, which explains how to use synchronous FIFO to realize multi-lane De-skew and complete the corresponding logic design. UVM and VIP technology are used to build a verification platform, the test results verify the correctness and feasibility of the design.Compared with other common solutions, the logic design has comprehensiveness, advantages and reusability.
