中圖分類號：TN401 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.223103 中文引用格式： 趙嘉禾,，宋潤泉,，許惟超，等. 基于OCP的輕量級多主從跨時鐘域片上總線設(shè)計[J]. 電子技術(shù)應(yīng)用,，2023,，49(2)：45-49. 英文引用格式： Zhao Jiahe，Song Runquan,，Xu Weichao,，et al. A clock domain crossing multi-master-slave lightweight on-chip bus based on OCP[J]. Application of Electronic Technique，2023,，49(2)：45-49.
A clock domain crossing multi-master-slave lightweight on-chip bus based on OCP
Zhao Jiahe,，Song Runquan，Xu Weichao,，Wang Yunhao,，Zhang Xuan
Shanghai Aerospace Electronic Technology Institute， Shanghai 201109,， China
Abstract： The open core protocol (OCP) bus can be applied to decouple IP core functions and the interfaces to realize the plug-and-play function. Aiming at the synchronization problem when the OCP is connected to asynchronous clock domain, a lightweight synchronization interface is developed, which not only synchronizes the control signals but also reduces the hardware consumption caused by data buffer across the clock domain. In view of the scalability of the point-to-point OCP bus, the enhanced clock-domain-crossing OCP bus is deployed on the AMBA High-performance Bus (AHB),，which is interconnected by the shared bus, in order to realize multi-master-slave multi-clock transmission. It is proved by simulation that the enhanced clock-domain-crossing OCP-AHB bus can transmit data correctly, which is able to be rapidly deployed in the next step.
Key words : system on chip；clock domain cross,；multiple master slave,；open core protocol
0 引言
片上系統(tǒng)（System on Chip，SoC）的出現(xiàn)允許設(shè)計者將完整的系統(tǒng)集成到一塊芯片上,。由于系統(tǒng)復(fù)雜度和市場帶來的壓力，設(shè)計者不會獨立開發(fā)完整的SoC,，而是傾向于復(fù)用已設(shè)計好的功能模塊或購買其他公司的知識產(chǎn)權(quán)（Intellectual Property,，IP）核，以便于在高層級構(gòu)建系統(tǒng)。SoC中的IP核通過片上總線相互連接,，片上總線的性能直接影響IP核互聯(lián)效率,。目前常用的片上總線標(biāo)準(zhǔn)包括高級微控制器總線結(jié)構(gòu)（Advanced Microcontroller Bus Architecture，AMBA）總線,、開放芯核協(xié)議（Open Core Protocol,，OCP）總線等[1]。
