摘要： PCIe接口是System on Chip (SoC）芯片上使用非常廣泛的一種高速接口,。因此,，在SoC芯片的Register Transfer Level(RTL)級(jí)設(shè)計(jì)開發(fā)階段，對(duì)PCIe接口設(shè)計(jì)的驗(yàn)證顯得尤為重要,，需要通過不同的驗(yàn)證平臺(tái)保證PCIe接口設(shè)計(jì)的功能正確性和性能穩(wěn)定性。對(duì)基于Cadence 硬件仿真器創(chuàng)建的PCIe接口驗(yàn)證平臺(tái)的方法進(jìn)行研究，并在某款SoC芯片上實(shí)現(xiàn)了該驗(yàn)證流程,。實(shí)踐表明，使用該方法能夠較快速地構(gòu)建驗(yàn)證平臺(tái),，提供較高的仿真測試性能,，同時(shí)支持多種調(diào)試手段，有效地完成驗(yàn)證目標(biāo),。
中圖分類號(hào)： TN47 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.209806 中文引用格式： 郝強(qiáng). 基于硬件仿真器的PCIe接口驗(yàn)證方法的研究和實(shí)現(xiàn)[J].電子技術(shù)應(yīng)用,，2020，46(8)：77-79. 英文引用格式： Hao Qiang. Research and implementation of verification method for PCIe interface based on emulator[J]. Application of Electronic Technique,，2020,，46(8)：77-79.
Research and implementation of verification method for PCIe interface based on emulator
Hao Qiang
Shanghai Hi-Performance IC Design Center，Shanghai 201204,，China
Abstract： The PCIe interface is a kind of high-speed interface widely used on system on chip(SoC). In the register transfer level(RTL) design and development stage of the SoC, it is particularly important to verify the design of the PCIe interface. Different verification platforms are needed to ensure the functional correctness and performance stability of the design. This paper focuses on the method of PCIe interface verification platform based on Cadence emulator, and realizes the verification method with a chip. The practice shows that this method can quickly build the verification platform, provide high emulation performance, support a variety of debugging methods, and effectively complete the verification objectives.
Key words : emulation,；PCIe；integrated circuit verification
