適用于Sigma-Delta ADC的多抽取率數(shù)字濾波器設計
2022年電子技術應用第1期
王 堯,卜 剛
南京航空航天大學 電子信息工程學院,江蘇 南京210000
摘要: 采用標準0.18 μm工藝,,設計了一種能改變抽取率并且適應不同信號帶寬的應用于Sigma-Delta模數(shù)轉換器的數(shù)字抽取濾波器。該濾波器采用多級抽取,,由級聯(lián)積分梳狀濾波器、補償濾波器和半帶濾波器組成,。實現(xiàn)的數(shù)字濾波器抽取率可以在64,、128,、256、512中變化,,并且補償濾波器和半帶濾波器的帶寬可調(diào)整,。濾波器版圖尺寸0.6 mm×0.6 mm。在1.98 V工作電壓下,,最大總功耗約為2 mW,最高信噪比達到110.5 dB,。當補償濾波器和半帶濾波器的通帶截止頻率根據(jù)帶寬選擇從最高降到最低時,,可分別節(jié)省56%和39%的功耗;當濾波器功耗降至最小69.63 μW時,,所能處理的帶寬為390.6 Hz,,信噪比為107.8 dB。
中圖分類號: TN492
文獻標識碼: A
DOI:10.16157/j.issn.0258-7998.211706
中文引用格式: 王堯,,卜剛. 適用于Sigma-Delta ADC的多抽取率數(shù)字濾波器設計[J].電子技術應用,,2022,48(1):89-93.
英文引用格式: Wang Yao,,Bu Gang. Design of multi-decimation rate digital filter for sigma-delta ADC[J]. Application of Electronic Technique,,2022,48(1):89-93.
文獻標識碼: A
DOI:10.16157/j.issn.0258-7998.211706
中文引用格式: 王堯,,卜剛. 適用于Sigma-Delta ADC的多抽取率數(shù)字濾波器設計[J].電子技術應用,,2022,48(1):89-93.
英文引用格式: Wang Yao,,Bu Gang. Design of multi-decimation rate digital filter for sigma-delta ADC[J]. Application of Electronic Technique,,2022,48(1):89-93.
Design of multi-decimation rate digital filter for sigma-delta ADC
Wang Yao,,Bu Gang
College of Electronic Information Engineering,,Nanjing University of Aeronautics and Astronautics,Nanjing 210000,,China
Abstract: Based on the standard 0.18 μm process, a digital decimation filter applied to the Sigma-Delta analog-to-digital converter is designed, which can change the decimation rate and adapt to different signal bandwidths. The filter adopts multi-stage decimation and consists of a cascaded integrator comb filter, a compensation filter and a half-band filter. The realized digital filter can be changed in the decimation rate of 64,,128,256 and 512. Compensation filters and half-band filters of different bandwidths are also designed. The filter area is 0.6 mm×0.6 mm. Under 1.98 V working voltage, the total maximum power consumption is about 2 mW, and the highest signal-to-noise ratio reaches 110.5 dB. When the passband frequency of the compensation filter and the half-band filter is selected according to the bandwidth from the highest to the lowest, it can save 61% and 53% of the power consumption respectively; When the filter power consumption being the smallest 69.63 μW, the bandwidth that can be processed is 390.6 Hz, and the signal-to-noise ratio is 107.8 dB.
Key words : digital decimation filter,;multiple decimation rate; low power consumption; multiple bandwidth
0 引言
現(xiàn)代信息技術飛速發(fā)展,,導致對模數(shù)轉換器(Analog-To-Digital Converter,ADC)的需求越來越大,,對其要求也越來越高,。而Sigma-delta ADC作為實現(xiàn)高分辨率ADC的方案被業(yè)界所認可。這種濾波器通過過采樣和噪聲整形技術提高信噪比,,在調(diào)制器之后需要濾波器來降低采樣率并濾除帶外噪聲,。采用多級結構是業(yè)內(nèi)的常用做法,因為單級結構的濾波器往往需要上千階,,實現(xiàn)困難,。本文采用多抽取率和多帶寬的濾波器結構,意在讓其適用于多種輸入信號帶寬下多種轉換精度的要求,。
本文詳細內(nèi)容請下載:http://forexkbc.com/resource/share/2000003915,。
作者信息:
王 堯,,卜 剛
(南京航空航天大學 電子信息工程學院,江蘇 南京210000)
此內(nèi)容為AET網(wǎng)站原創(chuàng),,未經(jīng)授權禁止轉載,。