《電子技術(shù)應(yīng)用》
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先進(jìn)工藝芯片填充冗余金屬后的時(shí)序偏差分析及修復(fù)
2022年電子技術(shù)應(yīng)用第6期
王秋實(shí),,孟少鵬,吳宏強(qiáng)
安徽芯紀(jì)元科技有限公司,,安徽 合肥230031
摘要: 在芯片物理設(shè)計(jì)的完成階段,,為了滿(mǎn)足設(shè)計(jì)規(guī)則中金屬密度要求,,需要填充冗余金屬,。增加的金屬層會(huì)產(chǎn)生額外的寄生電容,導(dǎo)致芯片的時(shí)序結(jié)果惡化,。40 nm以上的工藝節(jié)點(diǎn)中,,這些額外增加的寄生電容對(duì)于時(shí)序的影響在0.12%左右,這個(gè)時(shí)序偏差甚至比靜態(tài)時(shí)序分析與SPICE仿真之間的誤差還小,,在芯片設(shè)計(jì)時(shí)通常忽略它,。然而在使用FinFET結(jié)構(gòu)的先進(jìn)工藝節(jié)點(diǎn)中,這個(gè)時(shí)序偏差必須要進(jìn)行修復(fù),。以一款FinFET結(jié)構(gòu)工藝的工業(yè)級(jí)DSP芯片為實(shí)例,,使用QRC工具對(duì)比了芯片填充冗余金屬前后寄生電容的變化;使用Tempus工具分析了芯片時(shí)序結(jié)果發(fā)生偏差的原因,;最后提出了一種基于Innovus平臺(tái)的時(shí)序偏差修復(fù)方法,,時(shí)序結(jié)果通過(guò)簽核驗(yàn)證,有效提高了時(shí)序收斂的效率,。
中圖分類(lèi)號(hào): TN47
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.212353
中文引用格式: 王秋實(shí),,孟少鵬,吳宏強(qiáng). 先進(jìn)工藝芯片填充冗余金屬后的時(shí)序偏差分析及修復(fù)[J].電子技術(shù)應(yīng)用,,2022,,48(6):42-44,49.
英文引用格式: Wang Qiushi,,Meng Shaopeng,,Wu Hongqiang. Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip[J]. Application of Electronic Technique,2022,,48(6):42-44,,49.
Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip
Wang Qiushi,Meng Shaopeng,,Wu Hongqiang
Anhui Siliepoch Technology Co.,,Ltd.,Hefei 230031,,China
Abstract: In the finish stage of the chip physical design, in order to meet the metal density design rules, dummy metal fill needs to be added. The dummy metal fill generates external parasitic capacitances, which will deteriorate chip timing results. In process nodes above 40 nm, timing deviation caused by these external parasitic capacitances is about 0.12%, even smaller than the mismatch between STA and SPICE simulation, we usually ignore it. However, this timing deviation must be repaired in advanced process nodes with FinFET structure. Taking a industrial DSP process chip with FinFET structure as an example, this paper uses QRC to compare the parasitic capacitance changes before and after adding dummy metal fill; uses Tempus to analyze the reasons for the timing deviation of the chip; finally proposes a method for repairing timing deviation based on Innovus, the timing result is verified by signoff. This method effectively improves the efficiency of timing closure.
Key words : advanced process node,;physical design;dummy metal fill,;parasitic capacitance,;timing repair

0 引言

    冗余金屬填充是一種可制造性設(shè)計(jì)(Design For Manufacturing,DFM)手段,,目的是為了減小芯片制造過(guò)程中化學(xué)機(jī)械拋光(Chemical Mechanical Polishing,,CMP)帶來(lái)的工藝偏差,提高芯片的成品率[1-2],。在金屬互連線(xiàn)平坦化過(guò)程中,,同時(shí)包含了化學(xué)作用和機(jī)械作用[3],,金屬和介質(zhì)材料本身的研磨速率不同以及金屬密度的不均勻就會(huì)造成金屬層的高低起伏,可能導(dǎo)致互連線(xiàn)短路,、斷路等異常結(jié)果,,從而導(dǎo)致整個(gè)芯片失效[4]。由于CMP工藝對(duì)圖形密度極為敏感,,業(yè)界通過(guò)添加冗余金屬圖形使芯片各個(gè)位置的金屬密度均勻分布,,以改善平坦化效果[5]

    在先進(jìn)工藝中,,版圖的密度梯度對(duì)芯片可制造性的影響越來(lái)越突出,,因此在冗余金屬填充過(guò)程中不僅需要考慮密度約束,也需要同時(shí)考慮密度梯度以及密度均勻性問(wèn)題[6],。在工藝進(jìn)入FinFET時(shí)代后,,冗余金屬填充還需要滿(mǎn)足雙曝光工藝的特點(diǎn),即所有的冗余金屬圖形需要均勻地被拆分到兩張不同的掩膜版上[7-8],。




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作者信息:

王秋實(shí),孟少鵬,,吳宏強(qiáng)

(安徽芯紀(jì)元科技有限公司,,安徽 合肥230031)




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