中圖分類號： TN722 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.212409 中文引用格式： 王家文,，潘文光. 一種高線性度的2.4 GHz CMOS功率放大器設(shè)計[J].電子技術(shù)應(yīng)用，2022,，48(12)：65-69. 英文引用格式： Wang Jiawen,，Pan Wenguang. Design of a 2.4 GHz CMOS power amplifier with high linearity[J]. Application of Electronic Technique，2022,，48(12)：65-69.
Design of a 2.4 GHz CMOS power amplifier with high linearity
Wang Jiawen1,，2，Pan Wenguang1,，2
1.School of Microelectronics,，University of Chinese Academy of Sciences，Beijing 100049,，China,； 2.Nanjing Zhongke Microelectronics Co.，Ltd.,，Nanjing 210018,，China
Abstract： In order to meet the market demand of low-cost, low-power consumption and high linearity of the Internet of Things, a 2.4 GHz power amplifier(PA) with high linearity is proposed. The power amplifier has a two-stage structure. In order to improve the gain while maintaining low static power consumption, the driver stage of the PA adopts a current multiplexing two-stage common source amplifier structure, uses a two-stage distortion cancellation method to reduce transconductance nonlinearity, and adopts diode linearization bias to compensate gain compression phenomenon caused by parasitic capacitance nonlinearity. The PA uses a 0.18 μm CMOS process. Simulation results show that at 2.4 GHz operating frequency, the PA has a small signal gain of 30 dB, an output 1 dB compression point of 21.7 dBm, a static power consumption of 53 mW, and a power-added efficiency peak of 31%.
Key words : power amplifier；current multiplexing,；distortion cancellation,；diode linearization bias
