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基于FPGA的晶圓級芯片封裝圖像序列配準(zhǔn)方法的設(shè)計(jì)與實(shí)現(xiàn)*
電子技術(shù)應(yīng)用
方俊杰,,吳澤一,黃煜蕭,,任青松,,王賡
上海交通大學(xué) 軟件學(xué)院,上海 200240
摘要: 針對未切割晶圓進(jìn)行封裝后的晶圓級芯片封裝(WLCSP),,12英寸晶圓以1 μm物理分辨率進(jìn)行自動(dòng)光學(xué)檢測(AOI)面臨大幅面,、高質(zhì)量成像和成像速度的技術(shù)挑戰(zhàn)。晶圓全局圖像需由多幅掃描生成的局部圖像序列拼接而成,,為實(shí)現(xiàn)圖像序列的高質(zhì)量,、高速配準(zhǔn),在FPGA中采用OpenCL實(shí)現(xiàn)相位相關(guān)法進(jìn)行四鄰域棋盤配準(zhǔn),。首先在構(gòu)建二維FFT和互功率譜函數(shù)內(nèi)核的基礎(chǔ)上,,采用雙端口緩存和行緩存的設(shè)備全局內(nèi)存對計(jì)算過程的頻譜數(shù)據(jù)進(jìn)行復(fù)用并應(yīng)用內(nèi)核通道級聯(lián)提高配準(zhǔn)速度,基于最小生成樹優(yōu)化配準(zhǔn)結(jié)果降低全局圖像坐標(biāo)計(jì)算的累積誤差,,并經(jīng)實(shí)際掃描圖像驗(yàn)證配準(zhǔn)算法及加速性能,。 關(guān)鍵詞:晶圓級芯片封裝;圖像配準(zhǔn),;FPGA,;OpenCL
中圖分類號:TN402 文獻(xiàn)標(biāo)志碼:A DOI: 10.16157/j.issn.0258-7998.234273
中文引用格式: 方俊杰,吳澤一,,黃煜蕭,,等. 基于FPGA的晶圓級芯片封裝圖像序列配準(zhǔn)方法的設(shè)計(jì)與實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用,2023,,49(12):90-97.
英文引用格式: Fang Junjie,,Wu Zeyi,Huang Yuxiao,,et al. Method of image sequence registration for wafer level chip scale packaging based on FPGA[J]. Application of Electronic Technique,,2023,,49(12):90-97.
Method of image sequence registration for wafer level chip scale packaging based on FPGA
Fang Junjie,Wu Zeyi,,Huang Yuxiao,,Ren Qingsong,Wang Geng
School of Software,, Shanghai Jiao Tong University,, Shanghai 200240, China
Abstract: The Wafer Level Chip Scale Packaging (WLCSP) of chips on 12-inch wafers without dicing poses significant technological challenges for automatic optical inspection (AOI) in terms of high-quality imaging and imaging speed. To achieve high-quality and high-speed registration of the image sequence, a local image sequence generated by multiple scans needs to be stitched together to form a global image of the wafer. To this end, a phase correlation method based on the four-neighborhood checkerboard registration is implemented using OpenCL in an FPGA to address the challenge. Initially, a two-dimensional Fast Fourier Transform (FFT) and cross-power spectrum function kernel are constructed. Then, dual-port and row-buffered device global memory are employed to reuse the computed spectral data and to apply kernel channel cascading to enhance the registration speed. Finally, the registration result is optimized using a minimum spanning tree algorithm to reduce the cumulative error of global image coordinate calculation. The proposed registration algorithm and its accelerated performance are verified using actual scanned images.
Key words : wafer level chip scale package,;image registration,;FPGA;OpenCL

0 引言

晶圓級芯片封裝(Wafer Level Chip Scale Packaging, WLCSP)是一種對尚未切割的整片晶圓進(jìn)行封裝的先進(jìn)封裝技術(shù),,該技術(shù)生產(chǎn)工序中僅切割合格的芯片顆粒到后續(xù)制造工序中[1],。工業(yè)制造中使用自動(dòng)光學(xué)檢測(Automatic Optical Inspection, AOI)技術(shù)對晶圓級芯片封裝的整片晶圓表面進(jìn)行缺陷檢測,過程中需獲取整片晶圓表面圖像,,需要高效的圖像生成與拼接技術(shù)支持,。

針對12英寸WLCSP的整片晶圓,以1 m物理分辨率精度獲取晶圓表面圖像,,其圖像具有幅面大,、精度高的特點(diǎn),整體像素?cái)?shù)量可達(dá)1011,,存在圖像生成空間占用大、圖像序列鄰接關(guān)系復(fù)雜,、整體算法計(jì)算量大的問題與挑戰(zhàn),。

掃描生成的局部圖像拼接前需進(jìn)行配準(zhǔn)以確定各相鄰圖像間的位置關(guān)系,圖像配準(zhǔn)主要有基于頻域,、基于灰度圖像及基于特征匹配的方法,。對于圖像序列,一維或二維排列的場景均存在,,上交大潘昕對機(jī)器人移動(dòng)采集的大視差鋼卷一維圖像序列進(jìn)行帶尺度約束的特征匹配并拼接得到鋼卷倉庫全局圖像[2],;德國英飛凌Singla等人對掃描電子顯微鏡采集的晶圓二維圖像序列結(jié)合三種配準(zhǔn)方法進(jìn)行局部配準(zhǔn),并利用最大似然估計(jì)的方法在拼接過程中最小化全局誤差,,從而得到納米尺度晶圓表面結(jié)構(gòu)幾何布局[3],。



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作者信息:

方俊杰,吳澤一,,黃煜蕭,,任青松,王賡

(上海交通大學(xué) 軟件學(xué)院,,上海 200240)





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