基于負載追蹤補償?shù)拇箅娏鱈DO設計
電子技術應用
朱琪,黃登華
中國電子科技集團公司第五十八研究所,,江蘇 無錫 214072
摘要: 提出一種有效提升大電流輸出應用的低壓差線性穩(wěn)壓器(LDO)環(huán)路穩(wěn)定性的技術,,采用負載追蹤補償方式消除電路輸出端與負載相關的極點對環(huán)路穩(wěn)定性的影響,且在維持環(huán)路低頻增益不變的前提下降低高頻下環(huán)路中節(jié)點阻抗,,從而達到同時提升輸出精度和優(yōu)化瞬態(tài)響應性能的目的,。采用TSMC 0.18 µm BCD工藝進行仿真驗證,結果表明電路最大輸出電流6 A,,在6 A/6 μs的負載突變情況下輸出電壓下沖為36.6 mV,,過沖為35.3 mV,穩(wěn)定時間小于56.3 μs,。全負載電流范圍內(nèi),,瞬態(tài)性能大幅提升。
中圖分類號:TN432 文獻標志碼:A DOI: 10.16157/j.issn.0258-7998.234217
中文引用格式: 朱琪,,黃登華. 基于負載追蹤補償?shù)拇箅娏鱈DO設計[J]. 電子技術應用,,2024,50(3):26-30.
英文引用格式: Zhu Qi,,Huang Denghua. Design of a high current LDO based on load tracking technology[J]. Application of Electronic Technique,,2024,50(3):26-30.
中文引用格式: 朱琪,,黃登華. 基于負載追蹤補償?shù)拇箅娏鱈DO設計[J]. 電子技術應用,,2024,50(3):26-30.
英文引用格式: Zhu Qi,,Huang Denghua. Design of a high current LDO based on load tracking technology[J]. Application of Electronic Technique,,2024,50(3):26-30.
Design of a high current LDO based on load tracking technology
Zhu Qi,,Huang Denghua
The 58th Research Institute of China Electronics Technology Group Corporation,, Wuxi 214072, China
Abstract: This paper presents an effective load tracking compensation scheme to improve the loop stability of high current low-dropout linear regulator (LDO). By the proposed technique, the influence of variable load on the loop stability is eliminated, besides the low frequency loop gain retains to high while the high frequency impedance is greatly attenuated, finally both high output precision and decent transient response performance is achieved simultaneously. Simulated by TSMC 0.18 µm BCD process, the results show that the circuit is capable of delivering load current up to 6 A. For a load step of 6 A/6 μs, the circuit has a maximum undershoot of 36.6 mV and a maximum overshoot of 35.3 mV, the stable time is less than 56.3 μs. The transient performance is greatly improved within the full load current range.
Key words : low-dropout linear regulator,;load tracking,;loop gain;transient response
引言
隨著5G通信和大數(shù)據(jù)計算的迅速發(fā)展,,大規(guī)模集成電路(如CPU,,DSP)工作電流可達安培級別[1]。當采用LDO為CPU/DSP供電時,,芯片內(nèi)各個模塊的通斷將導致LDO負載電流發(fā)生突變,,從而使LDO的輸出電壓產(chǎn)生毛刺,最終引起CPU/DSP整體功能異常,,因此如何設計具有大電流輸出能力和良好瞬態(tài)性能的LDO具有重要研究意義[2-4],。
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作者信息:
朱琪,黃登華
中國電子科技集團公司第五十八研究所
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