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基于信號(hào)與電源完整性的有效分析優(yōu)化2.5D-3D的設(shè)計(jì)
2021年電子技術(shù)應(yīng)用第8期
何永松1,,秦祖立2,,林 麟1,吳 凱1
1.上海燧原科技有限公司,,上海200000,;2.上海鏗騰電子科技有限公司,上海200000
摘要: HBM(高帶寬內(nèi)存)存儲(chǔ)系統(tǒng)與傳統(tǒng)的DRAM接口相比,,具有高速率和低功耗特性,。在2.5D/3D的設(shè)計(jì)中,隨著HBM速率的提高,,對(duì)信號(hào)與電源完整性的設(shè)計(jì)的考量越來越重要,,如何通過有效的仿真指導(dǎo)產(chǎn)品的設(shè)計(jì)是一個(gè)挑戰(zhàn)。首先從信號(hào)完整性的角度討論了設(shè)計(jì)的考量點(diǎn),,其次從電源完整性的角度討論電源噪聲在高速傳輸信號(hào)中的影響,,并提出了如何仿真與預(yù)測(cè)大量同步開關(guān)噪聲等電源噪聲對(duì)眼圖的影響,最后基于芯片的測(cè)試結(jié)果對(duì)比仿真,,給出結(jié)論,。
中圖分類號(hào): TN402
文獻(xiàn)標(biāo)識(shí)碼: A
DOI:10.16157/j.issn.0258-7998.219806
中文引用格式: 何永松,秦祖立,,林麟,,等. 基于信號(hào)與電源完整性的有效分析優(yōu)化2.5D-3D的設(shè)計(jì)[J].電子技術(shù)應(yīng)用,2021,,47(8):64-67,,71.
英文引用格式: He Yongsong,Qin Zuli,Lin Lin,,et al. Optimizing 2.5D/3D IC design with efficient power and signal integrity analysis[J]. Application of Electronic Technique,,2021,47(8):64-67,,71.
Optimizing 2.5D/3D IC design with efficient power and signal integrity analysis
He Yongsong1,,Qin Zuli2,Lin Lin1,,Wu Kai1
1.Shanghai Enflame Technology,,Shanghai 200000,China,;2.Cadence Shanghai,,Shanghai 200000,China
Abstract: Compared with the traditional DRAM interface, the HBM(High Bandwidth Memory) storage system has the characteristics of high speed and low power consumption. In the design of 2.5D/3D, as the rate of HBM increases, the design considerations of signal and power integrity are becoming more and more important. How to guide the design of products through effective simulation is a challenge. The article firstly discusses design considerations from the perspective of signal integrity, then discusses the impact of power supply noise on high-speed transmission signals from the perspective of power integrity and proposes how to simulate and predict the effects of Simultaneous Switch noises. Finally based on the silicon chip, simulations have well correlated and verified by test results.
Key words : 2.5D/3D design,;signal integrity,;power integrity;SSN,;voltage noise prediction


0 引言

高帶寬內(nèi)存(High Bandwidth Memory,,HBM)存儲(chǔ)系統(tǒng)已成為某些超級(jí)計(jì)算機(jī)中用于高性能圖形加速、網(wǎng)絡(luò)設(shè)備以及高性能數(shù)據(jù)中心的最廣泛使用的存儲(chǔ)器件,。與傳統(tǒng)的存儲(chǔ)器接口相比,,HBM可實(shí)現(xiàn)更高的帶寬,同時(shí)消耗更少的功耗,。HBM廣泛應(yīng)用于高級(jí)封裝中,,結(jié)合中介層基板芯片(Interposer),實(shí)現(xiàn)存儲(chǔ)器的數(shù)據(jù)讀寫,。而Interposer的設(shè)計(jì)隨著HBM的速率上升,,信號(hào)完整性(SI)和電源完整性(PI)帶來的挑戰(zhàn)越來越大。Interposer的設(shè)計(jì)人員在初始設(shè)計(jì)時(shí),,為了克服SI和PI的挑戰(zhàn),,需要有效的仿真方法學(xué)指導(dǎo)設(shè)計(jì)。本文從SI和PI角度討論如何設(shè)計(jì)仿真,,并通過實(shí)測(cè)芯片驗(yàn)證仿真方法學(xué)的可靠性,。




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作者信息:

何永松1,,秦祖立2,,林  麟1,,吳  凱1

(1.上海燧原科技有限公司,,上海200000;2.上海鏗騰電子科技有限公司,上海200000)




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